* "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
*/
static unsigned
-swizzle_to_scs(GLenum swizzle)
+swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
{
switch (swizzle) {
case SWIZZLE_X:
return HSW_SCS_RED;
case SWIZZLE_Y:
- return HSW_SCS_GREEN;
+ return need_green_to_blue ? HSW_SCS_BLUE : HSW_SCS_GREEN;
case SWIZZLE_Z:
return HSW_SCS_BLUE;
case SWIZZLE_W:
}
}
+static void
+gen7_emit_buffer_surface_state(struct brw_context *brw,
+ uint32_t *out_offset,
+ drm_intel_bo *bo,
+ unsigned buffer_offset,
+ unsigned surface_format,
+ unsigned buffer_size,
+ unsigned pitch,
+ unsigned mocs)
+{
+ uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 8 * 4, 32, out_offset);
+ memset(surf, 0, 8 * 4);
+
+ surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
+ surface_format << BRW_SURFACE_FORMAT_SHIFT |
+ BRW_SURFACE_RC_READ_WRITE;
+ surf[1] = (bo ? bo->offset : 0) + buffer_offset; /* reloc */
+ surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
+ SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
+ surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
+ (pitch - 1);
+
+ surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
+
+ if (brw->is_haswell) {
+ surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
+ SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+ SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
+ SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
+ }
+
+ /* Emit relocation to surface contents */
+ if (bo) {
+ drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
+ bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER, 0);
+ }
+
+ gen7_check_surface_setup(surf, false /* is_render_target */);
+}
static void
gen7_update_buffer_texture_surface(struct gl_context *ctx,
drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
gl_format format = tObj->_BufferObjectFormat;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, surf_offset);
- memset(surf, 0, 8 * 4);
-
uint32_t surface_format = brw_format_for_mesa_format(format);
if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
_mesa_problem(NULL, "bad format %s for texture buffer\n",
_mesa_get_format_name(format));
}
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
-
- if (bo) {
- surf[1] = bo->offset; /* reloc */
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- bo, 0,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- int texel_size = _mesa_get_format_bytes(format);
- int w = (intel_obj->Base.Size / texel_size) - 1;
-
- /* note that these differ from GEN6 */
- surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
- SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */
- surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */
- (texel_size - 1);
- }
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
+ int texel_size = _mesa_get_format_bytes(format);
+ int w = intel_obj ? intel_obj->Base.Size / texel_size : 0;
+
+ gen7_emit_buffer_surface_state(brw,
+ surf_offset,
+ bo,
+ 0,
+ surface_format,
+ w,
+ texel_size,
+ 0 /* mocs */);
}
static void
gen7_update_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *surf_offset)
+ uint32_t *surf_offset,
+ bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
- struct intel_texture_image *intel_image = intel_texture_image(firstImage);
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
if (tObj->Target == GL_TEXTURE_BUFFER) {
tObj->DepthMode,
sampler->sRGBDecode);
+ if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
+ tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
+
surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
tex_format << BRW_SURFACE_FORMAT_SHIFT |
gen7_surface_tiling_mode(mt->region->tiling) |
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
+ SET_FIELD(tObj->BaseLevel - mt->first_level,
+ GEN7_SURFACE_MIN_LOD) |
/* mip count */
- (intelObj->_MaxLevel - intel_image->mt->first_level));
+ (intelObj->_MaxLevel - tObj->BaseLevel));
if (brw->is_haswell) {
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
const int swizzle = unlikely(alpha_depth)
? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
+ const bool need_scs_green_to_blue = for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
+
surf[7] =
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
+ SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
+ SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
+ SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
+ SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
}
/* Emit relocation to surface contents */
{
uint32_t stride = dword_pitch ? 4 : 16;
uint32_t elements = ALIGN(size, stride) / stride;
- const GLint w = elements - 1;
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
- memset(surf, 0, 8 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
-
- assert(bo);
- surf[1] = bo->offset + offset; /* reloc */
-
- /* note that these differ from GEN6 */
- surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
- (stride - 1);
-
- if (brw->is_haswell) {
- surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
- }
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- bo, offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
- gen7_check_surface_setup(surf, false /* is_render_target */);
+ gen7_emit_buffer_surface_state(brw,
+ out_offset,
+ bo,
+ offset,
+ BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
+ elements,
+ stride,
+ 0 /* mocs */);
}
/**
void
gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
{
- const int w = brw->shader_time.bo->size - 1;
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
- memset(surf, 0, 8 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
-
- surf[1] = brw->shader_time.bo->offset; /* reloc */
-
- /* note that these differ from GEN6 */
- surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH);
-
- /* Unlike texture or renderbuffer surfaces, we only do untyped operations
- * on the shader_time surface, so there's no need to set HSW channel
- * overrides.
- */
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- brw->shader_time.bo, 0,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
+ gen7_emit_buffer_surface_state(brw,
+ out_offset,
+ brw->shader_time.bo,
+ 0,
+ BRW_SURFACEFORMAT_RAW,
+ brw->shader_time.bo->size,
+ 1,
+ 0 /* mocs */);
}
static void
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
+ uint32_t surf_index =
+ brw->wm.prog_data->binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
- &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]);
+ &brw->wm.base.surf_offset[surf_index]);
memset(surf, 0, 8 * 4);
/* From the Ivybridge PRM, Volume 4, Part 1, page 65,
GLenum gl_target = rb->TexImage ?
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
- uint32_t surf_index = SURF_INDEX_DRAW(unit);
+ uint32_t surf_index =
+ brw->wm.prog_data->binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
&brw->wm.base.surf_offset[surf_index]);
projects / mesa.git / blobdiff