#include "main/blend.h"
#include "main/samplerobj.h"
#include "main/texformat.h"
+#include "main/teximage.h"
#include "program/prog_parameter.h"
+#include "program/prog_instruction.h"
#include "intel_mipmap_tree.h"
#include "intel_batchbuffer.h"
#include "brw_defines.h"
#include "brw_wm.h"
-/**
- * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
- * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
- */
-static unsigned
-swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
-{
- switch (swizzle) {
- case SWIZZLE_X:
- return HSW_SCS_RED;
- case SWIZZLE_Y:
- return need_green_to_blue ? HSW_SCS_BLUE : HSW_SCS_GREEN;
- case SWIZZLE_Z:
- return HSW_SCS_BLUE;
- case SWIZZLE_W:
- return HSW_SCS_ALPHA;
- case SWIZZLE_ZERO:
- return HSW_SCS_ZERO;
- case SWIZZLE_ONE:
- return HSW_SCS_ONE;
- }
-
- assert(!"Should not get here: invalid swizzle mode");
- return HSW_SCS_ZERO;
-}
-
-uint32_t
-gen7_surface_tiling_mode(uint32_t tiling)
-{
- switch (tiling) {
- case I915_TILING_X:
- return GEN7_SURFACE_TILING_X;
- case I915_TILING_Y:
- return GEN7_SURFACE_TILING_Y;
- default:
- return GEN7_SURFACE_TILING_NONE;
- }
-}
-
-
-uint32_t
-gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
-{
- uint32_t ss4 = 0;
-
- if (num_samples > 4)
- ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
- else if (num_samples > 1)
- ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
- else
- ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
-
- if (layout == INTEL_MSAA_LAYOUT_IMS)
- ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
- else
- ss4 |= GEN7_SURFACE_MSFMT_MSS;
-
- return ss4;
-}
-
-
-void
-gen7_set_surface_mcs_info(struct brw_context *brw,
- uint32_t *surf,
- uint32_t surf_offset,
- const struct intel_mipmap_tree *mcs_mt,
- bool is_render_target)
-{
- /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
- *
- * "The MCS surface must be stored as Tile Y."
- */
- assert(mcs_mt->region->tiling == I915_TILING_Y);
-
- /* Compute the pitch in units of tiles. To do this we need to divide the
- * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
- */
- unsigned pitch_tiles = mcs_mt->region->pitch / 128;
-
- /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
- * GPU address of the MCS buffer; the lower 12 bits contain other control
- * information. Since buffer addresses are always on 4k boundaries (and
- * thus have their lower 12 bits zero), we can use an ordinary reloc to do
- * the necessary address translation.
- */
- assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
-
- surf[6] = GEN7_SURFACE_MCS_ENABLE |
- SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
- mcs_mt->region->bo->offset;
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- surf_offset + 6 * 4,
- mcs_mt->region->bo,
- surf[6] & 0xfff,
- is_render_target ? I915_GEM_DOMAIN_RENDER
- : I915_GEM_DOMAIN_SAMPLER,
- is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
-}
-
-
void
gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
{
}
}
-static void
-gen7_emit_buffer_surface_state(struct brw_context *brw,
- uint32_t *out_offset,
- drm_intel_bo *bo,
- unsigned buffer_offset,
- unsigned surface_format,
- unsigned buffer_size,
- unsigned pitch,
- unsigned mocs)
-{
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
- memset(surf, 0, 8 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
- surf[1] = (bo ? bo->offset : 0) + buffer_offset; /* reloc */
- surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
- (pitch - 1);
-
- surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
-
- if (brw->is_haswell) {
- surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
- }
-
- /* Emit relocation to surface contents */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER, 0);
- }
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-
-static void
-gen7_update_buffer_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset)
-{
- struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_buffer_object *intel_obj =
- intel_buffer_object(tObj->BufferObject);
- drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
- gl_format format = tObj->_BufferObjectFormat;
-
- uint32_t surface_format = brw_format_for_mesa_format(format);
- if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
- _mesa_problem(NULL, "bad format %s for texture buffer\n",
- _mesa_get_format_name(format));
- }
-
- int texel_size = _mesa_get_format_bytes(format);
- int w = intel_obj ? intel_obj->Base.Size / texel_size : 0;
-
- gen7_emit_buffer_surface_state(brw,
- surf_offset,
- bo,
- 0,
- surface_format,
- w,
- texel_size,
- 0 /* mocs */);
-}
-
-static void
-gen7_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset,
- bool for_gather)
-{
- struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- gen7_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, surf_offset);
- memset(surf, 0, 8 * 4);
-
- uint32_t tex_format = translate_tex_format(brw,
- mt->format,
- tObj->DepthMode,
- sampler->sRGBDecode);
-
- if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
- tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
-
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
- gen7_surface_tiling_mode(mt->region->tiling) |
- BRW_SURFACE_CUBEFACE_ENABLES;
-
- if (mt->align_h == 4)
- surf[0] |= GEN7_SURFACE_VALIGN_4;
- if (mt->align_w == 8)
- surf[0] |= GEN7_SURFACE_HALIGN_8;
-
- if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
- surf[0] |= GEN7_SURFACE_IS_ARRAY;
-
- if (mt->array_spacing_lod0)
- surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
-
- surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
-
- surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
- ((intelObj->mt->region->pitch) - 1);
-
- surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
-
- surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
- SET_FIELD(tObj->BaseLevel - mt->first_level,
- GEN7_SURFACE_MIN_LOD) |
- /* mip count */
- (intelObj->_MaxLevel - tObj->BaseLevel));
-
- if (brw->is_haswell) {
- /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
- * texturing functions that return a float, as our code generation always
- * selects the .x channel (which would always be 0).
- */
- const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
- (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
- firstImage->_BaseFormat == GL_DEPTH_STENCIL);
-
- const int swizzle = unlikely(alpha_depth)
- ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
-
- const bool need_scs_green_to_blue = for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
-
- surf[7] =
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
- }
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- intelObj->mt->region->bo,
- surf[1] - intelObj->mt->region->bo->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-
-/**
- * Create the constant buffer surface. Vertex/fragment shader constants will
- * be read from this buffer with Data Port Read instructions/messages.
- */
-static void
-gen7_create_constant_surface(struct brw_context *brw,
- drm_intel_bo *bo,
- uint32_t offset,
- uint32_t size,
- uint32_t *out_offset,
- bool dword_pitch)
-{
- uint32_t stride = dword_pitch ? 4 : 16;
- uint32_t elements = ALIGN(size, stride) / stride;
-
- gen7_emit_buffer_surface_state(brw,
- out_offset,
- bo,
- offset,
- BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
- elements,
- stride,
- 0 /* mocs */);
-}
-
/**
- * Create a surface for shader time.
+ * Creates a null surface.
+ *
+ * This is used when the shader doesn't write to any color output. An FB
+ * write to target 0 will still be emitted, because that's how the thread is
+ * terminated (and computed depth is returned), so we need to have the
+ * hardware discard the target 0 color output..
*/
-void
-gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
-{
- gen7_emit_buffer_surface_state(brw,
- out_offset,
- brw->shader_time.bo,
- 0,
- BRW_SURFACEFORMAT_RAW,
- brw->shader_time.bo->size,
- 1,
- 0 /* mocs */);
-}
-
static void
-gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
+gen7_emit_null_surface_state(struct brw_context *brw,
+ unsigned width,
+ unsigned height,
+ unsigned samples,
+ uint32_t *out_offset)
{
/* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
* Notes):
* depth buffer’s corresponding state for all render target surfaces,
* including null.
*/
- struct gl_context *ctx = &brw->ctx;
-
- /* _NEW_BUFFERS */
- const struct gl_framebuffer *fb = ctx->DrawBuffer;
-
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
- &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]);
+ out_offset);
memset(surf, 0, 8 * 4);
/* From the Ivybridge PRM, Volume 4, Part 1, page 65,
BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
GEN7_SURFACE_TILING_Y;
- surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
-
- gen7_check_surface_setup(surf, true /* is_render_target */);
-}
-
-/**
- * Sets up a surface state structure to point at the given region.
- * While it is only used for the front/back buffer currently, it should be
- * usable for further buffers when doing ARB_draw_buffer support.
- */
-static void
-gen7_update_renderbuffer_surface(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned int unit)
-{
- struct gl_context *ctx = &brw->ctx;
- struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- struct intel_region *region = irb->mt->region;
- uint32_t format;
- /* _NEW_BUFFERS */
- gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
- uint32_t surftype;
- bool is_array = false;
- int depth = MAX2(rb->Depth, 1);
- int min_array_element;
- const uint8_t mocs = GEN7_MOCS_L3;
- GLenum gl_target = rb->TexImage ?
- rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
-
- uint32_t surf_index = SURF_INDEX_DRAW(unit);
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
- &brw->wm.base.surf_offset[surf_index]);
- memset(surf, 0, 8 * 4);
-
- intel_miptree_used_for_rendering(irb->mt);
-
- /* Render targets can't use IMS layout */
- assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
-
- assert(brw_render_target_supported(brw, rb));
- format = brw->render_target_format[rb_format];
- if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
- _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
- __FUNCTION__, _mesa_get_format_name(rb_format));
- }
-
- switch (gl_target) {
- case GL_TEXTURE_CUBE_MAP_ARRAY:
- case GL_TEXTURE_CUBE_MAP:
- surftype = BRW_SURFACE_2D;
- is_array = true;
- depth *= 6;
- break;
- default:
- surftype = translate_tex_target(gl_target);
- is_array = _mesa_tex_target_is_array(gl_target);
- break;
- }
-
- if (layered) {
- min_array_element = 0;
- } else if (irb->mt->num_samples > 1) {
- min_array_element = irb->mt_layer / irb->mt->num_samples;
- } else {
- min_array_element = irb->mt_layer;
- }
-
- surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
- format << BRW_SURFACE_FORMAT_SHIFT |
- (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
- : GEN7_SURFACE_ARYSPC_FULL) |
- gen7_surface_tiling_mode(region->tiling);
-
- if (irb->mt->align_h == 4)
- surf[0] |= GEN7_SURFACE_VALIGN_4;
- if (irb->mt->align_w == 8)
- surf[0] |= GEN7_SURFACE_HALIGN_8;
-
- if (is_array) {
- surf[0] |= GEN7_SURFACE_IS_ARRAY;
- }
-
- surf[1] = region->bo->offset;
-
- assert(brw->has_surface_tile_offset);
-
- surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
- (irb->mt_level - irb->mt->first_level);
-
- surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
-
- surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
- (region->pitch - 1);
-
- surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
- min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
- (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
-
- if (irb->mt->mcs_mt) {
- gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index],
- irb->mt->mcs_mt, true /* is RT */);
- }
-
- surf[7] = irb->mt->fast_clear_color_value;
-
- if (brw->is_haswell) {
- surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
- }
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- region->bo,
- surf[1] - region->bo->offset,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+ SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
gen7_check_surface_setup(surf, true /* is_render_target */);
}
void
gen7_init_vtable_surface_functions(struct brw_context *brw)
{
- brw->vtbl.update_texture_surface = gen7_update_texture_surface;
- brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
- brw->vtbl.update_null_renderbuffer_surface =
- gen7_update_null_renderbuffer_surface;
- brw->vtbl.create_constant_surface = gen7_create_constant_surface;
+ brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
+ brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
}
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