* IN THE SOFTWARE.
*/
#include "main/mtypes.h"
+#include "main/blend.h"
#include "main/samplerobj.h"
+#include "main/texformat.h"
#include "program/prog_parameter.h"
#include "intel_mipmap_tree.h"
int texel_size = _mesa_get_format_bytes(format);
int w = intel_obj->Base.Size / texel_size;
+
+ /* note that these differ from GEN6 */
surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
- SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); /* 19:7 */
- surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | /* bits 26:20 */
+ SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */
+ surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */
(texel_size - 1);
}
struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- int width, height, depth;
uint32_t tile_x, tile_y;
if (tObj->Target == GL_TEXTURE_BUFFER) {
return;
}
- /* We don't support MSAA for textures. */
- assert(!mt->array_spacing_lod0);
- assert(mt->num_samples <= 1);
-
- intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
-
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, &binding_table[surf_index]);
memset(surf, 0, 8 * 4);
- uint32_t tex_format = translate_tex_format(mt->format,
- firstImage->InternalFormat,
+ uint32_t tex_format = translate_tex_format(intel,
+ mt->format,
tObj->DepthMode,
sampler->sRGBDecode);
if (mt->align_w == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
+ if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
surf[0] |= GEN7_SURFACE_IS_ARRAY;
+ if (mt->array_spacing_lod0)
+ surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
+
surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
+ surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
+ &tile_x, &tile_y);
- surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
+ surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
+ SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
+ surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
((intelObj->mt->region->pitch) - 1);
- intel_miptree_get_tile_offsets(intelObj->mt, 0, 0, &tile_x, &tile_y);
+ surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
binding_table[surf_index] + 4,
- intelObj->mt->region->bo, intelObj->mt->offset,
+ intelObj->mt->region->bo,
+ surf[1] - intelObj->mt->region->bo->offset,
I915_GEM_DOMAIN_SAMPLER, 0);
gen7_check_surface_setup(surf, false /* is_render_target */);
gen7_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
- int width,
- uint32_t *out_offset)
+ uint32_t size,
+ uint32_t *out_offset,
+ bool dword_pitch)
{
struct intel_context *intel = &brw->intel;
- const GLint w = width - 1;
+ uint32_t stride = dword_pitch ? 4 : 16;
+ uint32_t elements = ALIGN(size, stride) / stride;
+ const GLint w = elements - 1;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, out_offset);
assert(bo);
surf[1] = bo->offset + offset; /* reloc */
+ /* note that these differ from GEN6 */
surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) |
- (16 - 1); /* stride between samples */
+ SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
+ surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
+ (stride - 1);
if (intel->is_haswell) {
surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
gen7_check_surface_setup(surf, false /* is_render_target */);
}
+/**
+ * Create a surface for shader time.
+ */
+void
+gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
+{
+ struct intel_context *intel = &brw->intel;
+ const int w = brw->shader_time.bo->size - 1;
+
+ uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 8 * 4, 32, out_offset);
+ memset(surf, 0, 8 * 4);
+
+ surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
+ BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT |
+ BRW_SURFACE_RC_READ_WRITE;
+
+ surf[1] = brw->shader_time.bo->offset; /* reloc */
+
+ /* note that these differ from GEN6 */
+ surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
+ SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
+ surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH);
+
+ /* Unlike texture or renderbuffer surfaces, we only do untyped operations
+ * on the shader_time surface, so there's no need to set HSW channel
+ * overrides.
+ */
+
+ /* Emit relocation to surface contents. Section 5.1.1 of the gen4
+ * bspec ("Data Cache") says that the data cache does not exist as
+ * a separate cache and is just the sampler cache.
+ */
+ drm_intel_bo_emit_reloc(intel->batch.bo,
+ *out_offset + 4,
+ brw->shader_time.bo, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+
+ gen7_check_surface_setup(surf, false /* is_render_target */);
+}
+
static void
gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
{
static void
gen7_update_renderbuffer_surface(struct brw_context *brw,
struct gl_renderbuffer *rb,
+ bool layered,
unsigned int unit)
{
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_region *region = irb->mt->region;
- uint32_t tile_x, tile_y;
uint32_t format;
- gl_format rb_format = intel_rb_format(irb);
+ /* _NEW_BUFFERS */
+ gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ uint32_t surftype;
+ bool is_array = false;
+ int depth = MAX2(rb->Depth, 1);
+ int min_array_element;
+ GLenum gl_target = rb->TexImage ?
+ rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, &brw->wm.surf_offset[unit]);
memset(surf, 0, 8 * 4);
+ intel_miptree_used_for_rendering(irb->mt);
+
/* Render targets can't use IMS layout */
assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
- switch (rb_format) {
- case MESA_FORMAT_SARGB8:
- /* _NEW_BUFFERS
- *
- * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
- * blend/update as sRGB.
- */
- if (ctx->Color.sRGBEnabled)
- format = brw_format_for_mesa_format(rb_format);
- else
- format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
+ assert(brw_render_target_supported(intel, rb));
+ format = brw->render_target_format[rb_format];
+ if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
+ _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+ __FUNCTION__, _mesa_get_format_name(rb_format));
+ }
+
+ switch (gl_target) {
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ surftype = BRW_SURFACE_2D;
+ is_array = true;
+ depth *= 6;
break;
default:
- assert(brw_render_target_supported(intel, rb));
- format = brw->render_target_format[rb_format];
- if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
- _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
- __FUNCTION__, _mesa_get_format_name(rb_format));
- }
+ surftype = translate_tex_target(gl_target);
+ is_array = _mesa_tex_target_is_array(gl_target);
break;
}
- surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
+ if (layered) {
+ min_array_element = 0;
+ } else if (irb->mt->num_samples > 1) {
+ min_array_element = irb->mt_layer / irb->mt->num_samples;
+ } else {
+ min_array_element = irb->mt_layer;
+ }
+
+ surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT |
(irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
: GEN7_SURFACE_ARYSPC_FULL) |
if (irb->mt->align_w == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- /* reloc */
- surf[1] = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
- region->bo->offset; /* reloc */
+ if (is_array) {
+ surf[0] |= GEN7_SURFACE_IS_ARRAY;
+ }
+
+ surf[1] = region->bo->offset;
assert(brw->has_surface_tile_offset);
- /* Note that the low bits of these fields are missing, so
- * there's the possibility of getting in trouble.
- */
- assert(tile_x % 4 == 0);
- assert(tile_y % 2 == 0);
- surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
- SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
- surf[2] = SET_FIELD(rb->Width - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(rb->Height - 1, GEN7_SURFACE_HEIGHT);
- surf[3] = region->pitch - 1;
+ surf[5] = irb->mt_level - irb->mt->first_level;
+
+ surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
+ SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
- surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout);
+ surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
+ (region->pitch - 1);
- if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
+ min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
+ (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
+
+ if (irb->mt->mcs_mt) {
gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
irb->mt->mcs_mt, true /* is RT */);
}
+ surf[7] = irb->mt->fast_clear_color_value;
+
if (intel->is_haswell) {
- surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
+ surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
+ SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+ SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
+ SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
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