(void) surface_array_spacing;
- /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
- * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Surface Array
- * Spacing:
+ /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
+ * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
*
* If Multisampled Surface Storage Format is MSFMT_MSS and Number of
* Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
&& is_multisampled)
assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
- /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
- * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
- * Surface Storage Format:
+ /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
+ * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
*
* All multisampled render target surfaces must have this field set to
* MSFMT_MSS.
assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
}
- /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
- * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
- * Surface Storage Format:
+ /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
+ * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
*
* If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
* is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
}
- /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
- * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
- * Surface Storage Format:
+ /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
+ * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
*
* If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
* ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
* following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
* R24_UNORM_X8_TYPELESS.
*
- * But also:
+ * But also (from the Programming Notes):
*
* This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
*/
static void
gen7_update_buffer_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
+ uint32_t *surf_offset)
{
struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = &brw->intel;
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_buffer_object *intel_obj =
intel_buffer_object(tObj->BufferObject);
gl_format format = tObj->_BufferObjectFormat;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &binding_table[surf_index]);
+ 8 * 4, 32, surf_offset);
memset(surf, 0, 8 * 4);
uint32_t surface_format = brw_format_for_mesa_format(format);
if (bo) {
surf[1] = bo->offset; /* reloc */
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
- */
drm_intel_bo_emit_reloc(brw->batch.bo,
- binding_table[surf_index] + 4,
+ *surf_offset + 4,
bo, 0,
I915_GEM_DOMAIN_SAMPLER, 0);
static void
gen7_update_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
+ uint32_t *surf_offset)
{
struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = &brw->intel;
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
+ struct intel_texture_image *intel_image = intel_texture_image(firstImage);
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- uint32_t tile_x, tile_y;
if (tObj->Target == GL_TEXTURE_BUFFER) {
- gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
+ gen7_update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &binding_table[surf_index]);
+ 8 * 4, 32, surf_offset);
memset(surf, 0, 8 * 4);
uint32_t tex_format = translate_tex_format(brw,
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
- surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
- &tile_x, &tile_y);
surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
- assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
- /* Note that the low bits of these fields are missing, so
- * there's the possibility of getting in trouble.
- */
- surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
- (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+ surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
/* mip count */
- (intelObj->_MaxLevel - tObj->BaseLevel));
+ (intelObj->_MaxLevel - intel_image->mt->first_level));
if (brw->is_haswell) {
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
- binding_table[surf_index] + 4,
+ *surf_offset + 4,
intelObj->mt->region->bo,
surf[1] - intelObj->mt->region->bo->offset,
I915_GEM_DOMAIN_SAMPLER, 0);
uint32_t *out_offset,
bool dword_pitch)
{
- struct intel_context *intel = &brw->intel;
uint32_t stride = dword_pitch ? 4 : 16;
uint32_t elements = ALIGN(size, stride) / stride;
const GLint w = elements - 1;
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
}
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
- */
drm_intel_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
bo, offset,
void
gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
{
- struct intel_context *intel = &brw->intel;
const int w = brw->shader_time.bo->size - 1;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
* overrides.
*/
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
- */
drm_intel_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
brw->shader_time.bo, 0,
* depth buffer’s corresponding state for all render target surfaces,
* including null.
*/
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &brw->wm.surf_offset[unit]);
+ uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
+ &brw->wm.surf_offset[SURF_INDEX_DRAW(unit)]);
memset(surf, 0, 8 * 4);
/* From the Ivybridge PRM, Volume 4, Part 1, page 65,
bool layered,
unsigned int unit)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_region *region = irb->mt->region;
uint32_t format;
bool is_array = false;
int depth = MAX2(rb->Depth, 1);
int min_array_element;
+ const uint8_t mocs = GEN7_MOCS_L3;
GLenum gl_target = rb->TexImage ?
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &brw->wm.surf_offset[unit]);
+ uint32_t surf_index = SURF_INDEX_DRAW(unit);
+
+ uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
+ &brw->wm.surf_offset[surf_index]);
memset(surf, 0, 8 * 4);
intel_miptree_used_for_rendering(irb->mt);
assert(brw->has_surface_tile_offset);
- surf[5] = irb->mt_level - irb->mt->first_level;
+ surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
+ (irb->mt_level - irb->mt->first_level);
surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
(depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
if (irb->mt->mcs_mt) {
- gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
+ gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[surf_index],
irb->mt->mcs_mt, true /* is RT */);
}
}
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.surf_offset[unit] + 4,
+ brw->wm.surf_offset[surf_index] + 4,
region->bo,
surf[1] - region->bo->offset,
I915_GEM_DOMAIN_RENDER,
projects / mesa.git / blobdiff