i965: Move intel_context::is_<platform> flags to brw_context.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_wm_surface_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 3164f994dd4c1691db8e2fc2c055d5dc15d15e5b..e1690a7982778050c6422ba113c38dd26ef7a07a 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -128,7 +128,7 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
              mcs_mt->region->bo->offset;
 
-   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+   drm_intel_bo_emit_reloc(brw->batch.bo,
                            surf_offset + 6 * 4,
                            mcs_mt->region->bo,
                            surf[6] & 0xfff,
@@ -264,7 +264,7 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx,
        * bspec ("Data Cache") says that the data cache does not exist as
        * a separate cache and is just the sampler cache.
        */
-      drm_intel_bo_emit_reloc(intel->batch.bo,
+      drm_intel_bo_emit_reloc(brw->batch.bo,
                              binding_table[surf_index] + 4,
                              bo, 0,
                              I915_GEM_DOMAIN_SAMPLER, 0);
@@ -295,7 +295,6 @@ gen7_update_texture_surface(struct gl_context *ctx,
    struct intel_mipmap_tree *mt = intelObj->mt;
    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-   int width, height, depth;
    uint32_t tile_x, tile_y;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
@@ -303,15 +302,12 @@ gen7_update_texture_surface(struct gl_context *ctx,
       return;
    }
 
-   intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
-
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
                                     8 * 4, 32, &binding_table[surf_index]);
    memset(surf, 0, 8 * 4);
 
-   uint32_t tex_format = translate_tex_format(intel,
+   uint32_t tex_format = translate_tex_format(brw,
                                               mt->format,
-                                              firstImage->InternalFormat,
                                               tObj->DepthMode,
                                               sampler->sRGBDecode);
 
@@ -325,7 +321,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
    if (mt->align_w == 8)
       surf[0] |= GEN7_SURFACE_HALIGN_8;
 
-   if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
+   if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 
    if (mt->array_spacing_lod0)
@@ -335,9 +331,9 @@ gen7_update_texture_surface(struct gl_context *ctx,
    surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
                                              &tile_x, &tile_y);
 
-   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
-   surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
+   surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
+   surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
              ((intelObj->mt->region->pitch) - 1);
 
    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
@@ -351,7 +347,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
               /* mip count */
               (intelObj->_MaxLevel - tObj->BaseLevel));
 
-   if (intel->is_haswell) {
+   if (brw->is_haswell) {
       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
        * texturing functions that return a float, as our code generation always
        * selects the .x channel (which would always be 0).
@@ -371,7 +367,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
    }
 
    /* Emit relocation to surface contents */
-   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+   drm_intel_bo_emit_reloc(brw->batch.bo,
                           binding_table[surf_index] + 4,
                           intelObj->mt->region->bo,
                            surf[1] - intelObj->mt->region->bo->offset,
@@ -414,7 +410,7 @@ gen7_create_constant_surface(struct brw_context *brw,
    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
              (stride - 1);
 
-   if (intel->is_haswell) {
+   if (brw->is_haswell) {
       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
@@ -425,7 +421,7 @@ gen7_create_constant_surface(struct brw_context *brw,
     * bspec ("Data Cache") says that the data cache does not exist as
     * a separate cache and is just the sampler cache.
     */
-   drm_intel_bo_emit_reloc(intel->batch.bo,
+   drm_intel_bo_emit_reloc(brw->batch.bo,
                           *out_offset + 4,
                           bo, offset,
                           I915_GEM_DOMAIN_SAMPLER, 0);
@@ -466,7 +462,7 @@ gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
     * bspec ("Data Cache") says that the data cache does not exist as
     * a separate cache and is just the sampler cache.
     */
-   drm_intel_bo_emit_reloc(intel->batch.bo,
+   drm_intel_bo_emit_reloc(brw->batch.bo,
                            *out_offset + 4,
                            brw->shader_time.bo, 0,
                            I915_GEM_DOMAIN_SAMPLER, 0);
@@ -550,7 +546,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    /* Render targets can't use IMS layout */
    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 
-   assert(brw_render_target_supported(intel, rb));
+   assert(brw_render_target_supported(brw, rb));
    format = brw->render_target_format[rb_format];
    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
@@ -597,7 +593,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 
    assert(brw->has_surface_tile_offset);
 
-   surf[5] = irb->mt_level;
+   surf[5] = irb->mt_level - irb->mt->first_level;
 
    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
@@ -614,14 +610,16 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
                                 irb->mt->mcs_mt, true /* is RT */);
    }
 
-   if (intel->is_haswell) {
-      surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
-                SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
-                SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
-                SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
+   surf[7] = irb->mt->fast_clear_color_value;
+
+   if (brw->is_haswell) {
+      surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
+                  SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+                  SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
+                  SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
    }
 
-   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+   drm_intel_bo_emit_reloc(brw->batch.bo,
                           brw->wm.surf_offset[unit] + 4,
                           region->bo,
                           surf[1] - region->bo->offset,
@@ -634,11 +632,9 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 void
 gen7_init_vtable_surface_functions(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
-   intel->vtbl.update_texture_surface = gen7_update_texture_surface;
-   intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
-   intel->vtbl.update_null_renderbuffer_surface =
+   brw->vtbl.update_texture_surface = gen7_update_texture_surface;
+   brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
+   brw->vtbl.update_null_renderbuffer_surface =
       gen7_update_null_renderbuffer_surface;
-   intel->vtbl.create_constant_surface = gen7_create_constant_surface;
+   brw->vtbl.create_constant_surface = gen7_create_constant_surface;
 }