i965/urb: fixes division by zero

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_blorp.c

diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index 720f5244ca2f7b89ce55057fe6e6b266eafceb52..a9a400d906631fea492e25a9042870c316b1a38d 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -77,7 +77,7 @@ gen8_blorp_emit_surface_state(struct brw_context *brw,
       surf[6] = SET_FIELD(surface->mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
                 SET_FIELD((surface->mt->mcs_mt->pitch / 128) - 1,
                           GEN8_SURFACE_AUX_PITCH) |
-                GEN8_SURFACE_AUX_MODE_MCS;
+                gen8_get_aux_mode(brw, mt);
    } else {
       surf[6] = 0;
    }
@@ -372,13 +372,11 @@ gen8_blorp_emit_ps_config(struct brw_context *brw,
                           const struct brw_blorp_params *params)
 {
    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
-   uint32_t dw3, dw5, dw6, dw7;
+   uint32_t dw3, dw5, dw6, dw7, ksp0, ksp2;
 
-   dw3 = dw5 = dw6 = dw7 = 0;
+   dw3 = dw5 = dw6 = dw7 = ksp0 = ksp2 = 0;
    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 
-   dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
-
    if (params->src.mt) {
       dw3 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
       dw3 |= 2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT; /* Two surfaces */
@@ -387,7 +385,16 @@ gen8_blorp_emit_ps_config(struct brw_context *brw,
    }
 
    dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
-   dw7 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
+   dw7 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
+   dw7 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
+
+   if (params->wm_prog_data->dispatch_8)
+      dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
+   if (params->wm_prog_data->dispatch_16)
+      dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
+
+   ksp0 = params->wm_prog_kernel;
+   ksp2 = params->wm_prog_kernel + params->wm_prog_data->ksp_offset_2;
 
    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
     * it implicitly scales for different GT levels (which have some # of PSDs).
@@ -404,16 +411,16 @@ gen8_blorp_emit_ps_config(struct brw_context *brw,
 
    BEGIN_BATCH(12);
    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
-   OUT_BATCH(params->wm_prog_kernel);
+   OUT_BATCH(ksp0);
    OUT_BATCH(0);
    OUT_BATCH(dw3);
    OUT_BATCH(0);
    OUT_BATCH(0);
    OUT_BATCH(dw6);
    OUT_BATCH(dw7);
+   OUT_BATCH(0); /* kernel 1 pointer */
    OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
+   OUT_BATCH(ksp2);
    OUT_BATCH(0);
    ADVANCE_BATCH();
 }
@@ -601,14 +608,28 @@ gen8_blorp_emit_surface_states(struct brw_context *brw,
       const struct brw_blorp_surface_info *surface = &params->src;
       struct intel_mipmap_tree *mt = surface->mt;
 
-      /* Textures are always sampled as 2D. */
+      /* If src is a 2D multisample array texture on Gen7+ using
+       * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src layer is the
+       * physical layer holding sample 0.  So, for example, if mt->num_samples
+       * == 4, then logical layer n corresponds to layer == 4*n.
+       *
+       * Multisampled depth and stencil surfaces have the samples interleaved
+       * (INTEL_MSAA_LAYOUT_IMS) and therefore the layer doesn't need
+       * adjustment.
+       */
+      const unsigned layer_divider =
+         (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+          mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
+         MAX2(mt->num_samples, 1) : 1;
+
+      /* Cube textures are sampled as 2D array. */
       const bool is_cube = mt->target == GL_TEXTURE_CUBE_MAP_ARRAY ||
                            mt->target == GL_TEXTURE_CUBE_MAP;
       const unsigned depth = (is_cube ? 6 : 1) * mt->logical_depth0;
       const GLenum target = is_cube ? GL_TEXTURE_2D_ARRAY : mt->target;
       const unsigned max_level = surface->level + mt->last_level + 1;
       const unsigned layer = mt->target != GL_TEXTURE_3D ?
-                                surface->layer / MAX2(mt->num_samples, 1) : 0;
+                                surface->layer / layer_divider : 0;
 
       brw->vtbl.emit_texture_surface_state(brw, mt, target,
                                            layer, layer + depth,
@@ -632,8 +653,7 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
 {
    uint32_t wm_bind_bo_offset = 0;
 
-   if (gen8_state_base_address.dirty.brw & brw->ctx.NewDriverState)
-      gen8_upload_state_base_address(brw);
+   brw_upload_state_base_address(brw);
 
    gen7_blorp_emit_cc_viewport(brw);
    gen7_l3_state.emit(brw);