#include "brw_state.h"
#include "brw_defines.h"
#include "brw_wm.h"
+#include "main/framebuffer.h"
/**
* Helper function to emit depth related command packets.
bool depth_writable,
struct intel_mipmap_tree *stencil_mt,
bool stencil_writable,
- uint32_t stencil_offset,
bool hiz,
uint32_t width,
uint32_t height,
return;
}
- intel_emit_depth_stall_flushes(brw);
+ brw_emit_depth_stall_flushes(brw);
/* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
BEGIN_BATCH(8);
} else {
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
- OUT_BATCH((depth_mt->hiz_mt->pitch - 1) | mocs_wb << 25);
- OUT_RELOC64(depth_mt->hiz_mt->bo,
+ OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
+ OUT_RELOC64(depth_mt->hiz_buf->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(depth_mt->hiz_mt->qpitch >> 2);
+ OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
ADVANCE_BATCH();
}
if (stencil_mt == NULL) {
- BEGIN_BATCH(5);
+ BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
(2 * stencil_mt->pitch - 1));
OUT_RELOC64(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- stencil_offset);
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
ADVANCE_BATCH();
}
case GL_TEXTURE_3D:
assert(mt);
depth = MAX2(mt->logical_depth0, 1);
+ surftype = translate_tex_target(gl_target);
+ break;
+ case GL_TEXTURE_1D_ARRAY:
+ case GL_TEXTURE_1D:
+ if (brw->gen >= 9) {
+ /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
+ * textures but it does allow pretending it's a 2D texture
+ * instead.
+ */
+ surftype = BRW_SURFACE_2D;
+ break;
+ }
/* fallthrough */
default:
surftype = translate_tex_target(gl_target);
emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
ctx->Depth.Mask != 0,
stencil_mt, ctx->Stencil._WriteEnabled,
- brw->depthstencil.stencil_offset,
hiz, width, height, depth, lod, min_array_element);
}
pma_fix_enable(const struct brw_context *brw)
{
const struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct gl_fragment_program *fp = brw->fragment_program;
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb =
intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
*/
const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
- /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
- * We always leave this set to EDSC_NORMAL (0).
+ /* BRW_NEW_FS_PROG_DATA:
+ * 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
*/
- const bool edsc_not_preps = true;
+ const bool edsc_not_preps = !brw->wm.prog_data->early_fragment_tests;
/* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
const bool pixel_shader_valid = true;
*/
const bool stencil_writes_enabled = ctx->Stencil._WriteEnabled;
- /* BRW_NEW_FRAGMENT_PROGRAM:
- * 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode == PSCDEPTH_OFF
+ /* BRW_NEW_FS_PROG_DATA:
+ * 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF
*/
const bool ps_computes_depth =
- (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) &&
- fp->FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
+ brw->wm.prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
- /* CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
- * CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
+ /* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
+ * BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
* _NEW_MULTISAMPLE: 3DSTATE_PS_BLEND::AlphaToCoverageEnable
* _NEW_COLOR: 3DSTATE_PS_BLEND::AlphaTestEnable
*
const bool kill_pixel =
brw->wm.prog_data->uses_kill ||
brw->wm.prog_data->uses_omask ||
- (ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToCoverage) ||
+ (_mesa_is_multisample_enabled(ctx) && ctx->Multisample.SampleAlphaToCoverage) ||
ctx->Color.AlphaEnabled;
/* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
(kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
}
-static void
-write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
+void
+gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
{
struct gl_context *ctx = &brw->ctx;
* Flush is also necessary.
*/
const uint32_t render_cache_flush =
- ctx->Stencil._WriteEnabled ? PIPE_CONTROL_WRITE_FLUSH : 0;
+ ctx->Stencil._WriteEnabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
gen8_emit_pma_stall_workaround(struct brw_context *brw)
{
uint32_t bits = 0;
+
+ if (brw->gen >= 9)
+ return;
+
if (pma_fix_enable(brw))
bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
- write_pma_stall_bits(brw, bits);
+ gen8_write_pma_stall_bits(brw, bits);
}
const struct brw_tracked_state gen8_pma_fix = {
_NEW_DEPTH |
_NEW_MULTISAMPLE |
_NEW_STENCIL,
- .brw = BRW_NEW_FRAGMENT_PROGRAM,
- .cache = CACHE_NEW_WM_PROG,
+ .brw = BRW_NEW_BLORP |
+ BRW_NEW_FS_PROG_DATA,
},
.emit = gen8_emit_pma_stall_workaround
};
return;
/* Disable the PMA stall fix since we're about to do a HiZ operation. */
- write_pma_stall_bits(brw, 0);
+ if (brw->gen == 8)
+ gen8_write_pma_stall_bits(brw, 0);
assert(mt->first_level == 0);
assert(mt->logical_depth0 >= 1);
uint32_t surface_width = ALIGN(mt->logical_width0, level == 0 ? 8 : 1);
uint32_t surface_height = ALIGN(mt->logical_height0, level == 0 ? 4 : 1);
+ /* From the documentation for 3DSTATE_WM_HZ_OP: "3DSTATE_MULTISAMPLE packet
+ * must be used prior to this packet to change the Number of Multisamples.
+ * This packet must not be used to change Number of Multisamples in a
+ * rendering sequence."
+ */
+ if (brw->num_samples != mt->num_samples) {
+ gen8_emit_3dstate_multisample(brw, mt->num_samples);
+ brw->NewGLState |= _NEW_MULTISAMPLE;
+ }
+
/* The basic algorithm is:
* - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
* 3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
brw_depth_format(brw, mt->format),
BRW_SURFACE_2D,
true, /* depth writes */
- NULL, false, 0, /* no stencil for now */
+ NULL, false, /* no stencil for now */
true, /* hiz */
surface_width,
surface_height,
*/
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->batch.workaround_bo, 0, 0, 0);
+ brw->workaround_bo, 0, 0, 0);
/* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
BEGIN_BATCH(5);
*
* Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
*/
- brw->state.dirty.mesa |= _NEW_DEPTH | _NEW_BUFFERS;
+ brw->NewGLState |= _NEW_DEPTH | _NEW_BUFFERS;
}
projects / mesa.git / blobdiff