i965/fs: Disable CSE optimization for untyped & typed surface reads

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_disable.c

diff --git a/src/mesa/drivers/dri/i965/gen8_disable.c b/src/mesa/drivers/dri/i965/gen8_disable.c
index e1e26c6ac8e102d34da4533b04a861167ce3376d..32508e377c94df433c659d20ad21271e51276776 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_disable.c
+++ b/src/mesa/drivers/dri/i965/gen8_disable.c
@@ -29,6 +29,14 @@
 static void
 disable_stages(struct brw_context *brw)
 {
+   BEGIN_BATCH(5);
+   OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+
    /* Disable the HS Unit */
    BEGIN_BATCH(11);
    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (11 - 2));
@@ -58,7 +66,7 @@ disable_stages(struct brw_context *brw)
 
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
-   OUT_BATCH(0);
+   OUT_BATCH(brw->hw_bt_pool.next_offset);
    ADVANCE_BATCH();
 
    /* Disable the TE */
@@ -84,21 +92,16 @@ disable_stages(struct brw_context *brw)
    OUT_BATCH(0);
    ADVANCE_BATCH();
 
-   BEGIN_BATCH(9);
-   OUT_BATCH(_3DSTATE_DS << 16 | (9 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
+   int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
+   BEGIN_BATCH(ds_pkt_len);
+   OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
+   for (int i = 0; i < ds_pkt_len - 1; i++)
+      OUT_BATCH(0);
    ADVANCE_BATCH();
 
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
-   OUT_BATCH(0);
+   OUT_BATCH(brw->hw_bt_pool.next_offset);
    ADVANCE_BATCH();
 
    BEGIN_BATCH(2);
@@ -111,7 +114,6 @@ const struct brw_tracked_state gen8_disable_stages = {
    .dirty = {
       .mesa  = 0,
       .brw   = BRW_NEW_CONTEXT,
-      .cache = 0,
    },
    .emit = disable_stages,
 };