gen8_emit_vertices(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
+ uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
brw_prepare_vertices(brw);
+ brw_prepare_shader_draw_parameters(brw);
- if (brw->vs.prog_data->uses_vertexid) {
+ if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid) {
unsigned vue = brw->vb.nr_enabled;
WARN_ONCE(brw->vs.prog_data->inputs_read & VERT_BIT_EDGEFLAG,
"Trying to insert VID/IID past 33rd vertex element, "
"need to reorder the vertex attrbutes.");
+ unsigned dw1 = 0;
+ if (brw->vs.prog_data->uses_vertexid) {
+ dw1 |= GEN8_SGVS_ENABLE_VERTEX_ID |
+ (2 << GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT) | /* .z channel */
+ (vue << GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT);
+ }
+
+ if (brw->vs.prog_data->uses_instanceid) {
+ dw1 |= GEN8_SGVS_ENABLE_INSTANCE_ID |
+ (3 << GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT) | /* .w channel */
+ (vue << GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT);
+ }
+
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
- OUT_BATCH(GEN8_SGVS_ENABLE_VERTEX_ID |
- (0 << GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT) | /* .x channel */
- (vue << GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT) |
- GEN8_SGVS_ENABLE_INSTANCE_ID |
- (1 << GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT) | /* .y channel */
- (vue << GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT));
+ OUT_BATCH(dw1);
+ ADVANCE_BATCH();
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
+ OUT_BATCH(brw->vb.nr_buffers | GEN8_VF_INSTANCING_ENABLE);
+ OUT_BATCH(0);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(2);
}
/* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
- if (brw->vb.nr_buffers) {
- assert(brw->vb.nr_buffers <= 33);
+ unsigned nr_buffers = brw->vb.nr_buffers + brw->vs.prog_data->uses_vertexid;
+ if (nr_buffers) {
+ assert(nr_buffers <= 33);
- perf_debug("Missing MOCS setup for 3DSTATE_VERTEX_BUFFERS.");
-
- BEGIN_BATCH(1 + 4*brw->vb.nr_buffers);
- OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
+ BEGIN_BATCH(1 + 4 * nr_buffers);
+ OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4 * nr_buffers - 1));
for (unsigned i = 0; i < brw->vb.nr_buffers; i++) {
struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
uint32_t dw0 = 0;
dw0 |= i << GEN6_VB0_INDEX_SHIFT;
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
dw0 |= buffer->stride << BRW_VB0_PITCH_SHIFT;
- dw0 |= BDW_MOCS_WB << 16;
+ dw0 |= mocs_wb << 16;
OUT_BATCH(dw0);
OUT_RELOC64(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
OUT_BATCH(buffer->bo->size);
}
+
+ if (brw->vs.prog_data->uses_vertexid) {
+ OUT_BATCH(brw->vb.nr_buffers << GEN6_VB0_INDEX_SHIFT |
+ GEN7_VB0_ADDRESS_MODIFYENABLE |
+ mocs_wb << 16);
+ OUT_RELOC64(brw->draw.draw_params_bo, I915_GEM_DOMAIN_VERTEX, 0,
+ brw->draw.draw_params_offset);
+ OUT_BATCH(brw->draw.draw_params_bo->size);
+ }
ADVANCE_BATCH();
}
- unsigned nr_elements = brw->vb.nr_enabled;
+ unsigned nr_elements = brw->vb.nr_enabled + brw->vs.prog_data->uses_vertexid;
/* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
* presumably for VertexID/InstanceID.
(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
}
+
+ if (brw->vs.prog_data->uses_vertexid) {
+ OUT_BATCH(GEN6_VE0_VALID |
+ brw->vb.nr_buffers << GEN6_VE0_INDEX_SHIFT |
+ BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
+ OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
+ (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
+ (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
+ (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
+ }
ADVANCE_BATCH();
for (unsigned i = 0; i < brw->vb.nr_enabled; i++) {
const struct brw_tracked_state gen8_vertices = {
.dirty = {
.mesa = _NEW_POLYGON,
- .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
- .cache = CACHE_NEW_VS_PROG,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_VERTICES |
+ BRW_NEW_VS_PROG_DATA,
},
.emit = gen8_emit_vertices,
};
gen8_emit_index_buffer(struct brw_context *brw)
{
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
+ uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
if (index_buffer == NULL)
return;
BEGIN_BATCH(5);
OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
- OUT_BATCH(brw_get_index_type(index_buffer->type) << 8 | BDW_MOCS_WB);
+ OUT_BATCH(brw_get_index_type(index_buffer->type) | mocs_wb);
OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
OUT_BATCH(brw->ib.bo->size);
ADVANCE_BATCH();
const struct brw_tracked_state gen8_index_buffer = {
.dirty = {
.mesa = 0,
- .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
- .cache = 0,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_INDEX_BUFFER,
},
.emit = gen8_emit_index_buffer,
};
.dirty = {
.mesa = 0,
.brw = BRW_NEW_PRIMITIVE,
- .cache = 0,
},
.emit = gen8_emit_vf_topology,
};