i965: Pass number of components explicitly to brw_untyped_atomic and _surface_read.

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_draw_upload.c

diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 9e8e24b4630473e62389ba7c2bd3166c9b02e838..1af90ecc6a448a17198e890543c70de19fbb9382 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -251,7 +251,7 @@ gen8_emit_index_buffer(struct brw_context *brw)
 
    BEGIN_BATCH(5);
    OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
-   OUT_BATCH(brw_get_index_type(index_buffer->type) << 8 | mocs_wb);
+   OUT_BATCH(brw_get_index_type(index_buffer->type) | mocs_wb);
    OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
    OUT_BATCH(brw->ib.bo->size);
    ADVANCE_BATCH();
@@ -262,7 +262,6 @@ const struct brw_tracked_state gen8_index_buffer = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
              BRW_NEW_INDEX_BUFFER,
-      .cache = 0,
    },
    .emit = gen8_emit_index_buffer,
 };
@@ -280,7 +279,6 @@ const struct brw_tracked_state gen8_vf_topology = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_PRIMITIVE,
-      .cache = 0,
    },
    .emit = gen8_emit_vf_topology,
 };