i965/vec4: Assign correct destination offset to rewritten instruction in register...
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_ds_state.c
index 95582ac44482400917978f4ca1640b21a09085ae..6f01abb76fe265682eaee017024d49c447906dd9 100644 (file)
@@ -52,7 +52,7 @@ gen8_upload_ds_state(struct brw_context *brw)
       if (prog_data->total_scratch) {
          OUT_RELOC64(stage_state->scratch_bo,
                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                     ffs(prog_data->total_scratch) - 11);
+                     ffs(stage_state->per_thread_scratch) - 11);
       } else {
          OUT_BATCH(0);
          OUT_BATCH(0);
@@ -69,9 +69,11 @@ gen8_upload_ds_state(struct brw_context *brw)
                  GEN7_DS_SIMD8_DISPATCH_ENABLE : 0) |
                 (tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ?
                  GEN7_DS_COMPUTE_W_COORDINATE_ENABLE : 0));
-      OUT_BATCH(SET_FIELD(vue_prog_data->cull_distance_mask |
-                          ctx->Transform.ClipPlanesEnabled,
-                          GEN8_DS_USER_CLIP_DISTANCE));
+      OUT_BATCH(SET_FIELD(ctx->Transform.ClipPlanesEnabled,
+                          GEN8_DS_USER_CLIP_DISTANCE) |
+                SET_FIELD(vue_prog_data->cull_distance_mask,
+                          GEN8_DS_USER_CULL_DISTANCE));
+
 
       if (brw->gen >= 9) {
          OUT_BATCH(0);