i965/urb: fixes division by zero

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_ds_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c
index a79e8aa020e0f3b86fab024afa3ffd1a5b201218..95582ac44482400917978f4ca1640b21a09085ae 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c
@@ -31,18 +31,18 @@ gen8_upload_ds_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
    const struct brw_stage_state *stage_state = &brw->tes.base;
-   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   /* BRW_NEW_TESS_PROGRAMS */
    bool active = brw->tess_eval_program;
-   assert(!active || brw->tess_ctrl_program);
 
    /* BRW_NEW_TES_PROG_DATA */
    const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data;
    const struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
    const struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
+   const int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
 
    if (active) {
-      BEGIN_BATCH(9);
-      OUT_BATCH(_3DSTATE_DS << 16 | (9 - 2));
+      BEGIN_BATCH(ds_pkt_len);
+      OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
       OUT_BATCH(stage_state->prog_offset);
       OUT_BATCH(0);
       OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
@@ -69,12 +69,19 @@ gen8_upload_ds_state(struct brw_context *brw)
                  GEN7_DS_SIMD8_DISPATCH_ENABLE : 0) |
                 (tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ?
                  GEN7_DS_COMPUTE_W_COORDINATE_ENABLE : 0));
-      OUT_BATCH(SET_FIELD(ctx->Transform.ClipPlanesEnabled,
+      OUT_BATCH(SET_FIELD(vue_prog_data->cull_distance_mask |
+                          ctx->Transform.ClipPlanesEnabled,
                           GEN8_DS_USER_CLIP_DISTANCE));
+
+      if (brw->gen >= 9) {
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+      }
+
       ADVANCE_BATCH();
    } else {
-      BEGIN_BATCH(9);
-      OUT_BATCH(_3DSTATE_DS << 16 | (9 - 2));
+      BEGIN_BATCH(ds_pkt_len);
+      OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -83,8 +90,15 @@ gen8_upload_ds_state(struct brw_context *brw)
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
+
+      if (brw->gen >= 9) {
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+      }
+
       ADVANCE_BATCH();
    }
+
    brw->tes.enabled = active;
 }
 
@@ -92,7 +106,8 @@ const struct brw_tracked_state gen8_ds_state = {
    .dirty = {
       .mesa  = 0,
       .brw   = BRW_NEW_BATCH |
-               BRW_NEW_TESS_EVAL_PROGRAM |
+               BRW_NEW_BLORP |
+               BRW_NEW_TESS_PROGRAMS |
                BRW_NEW_TES_PROG_DATA,
    },
    .emit = gen8_upload_ds_state,