i965/state: Don't use brw->state.dirty.brw

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 464138886ef962853cc56bfcc9a973b3ab557dd7..88e425fa582be4b5b779cc78f5a5dbcc172f0e7e 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -31,27 +31,28 @@
  */
 static void upload_state_base_address(struct brw_context *brw)
 {
-   perf_debug("Missing MOCS setup for STATE_BASE_ADDRESS.");
+   uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+   int pkt_len = brw->gen >= 9 ? 19 : 16;
 
-   BEGIN_BATCH(16);
-   OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2));
+   BEGIN_BATCH(pkt_len);
+   OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
    /* General state base address: stateless DP read/write requests */
+   OUT_BATCH(mocs_wb << 4 | 1);
    OUT_BATCH(0);
-   OUT_BATCH(BDW_MOCS_WB << 2 | 1);
-   OUT_BATCH(BDW_MOCS_WB << 16);
+   OUT_BATCH(mocs_wb << 16);
    /* Surface state base address: */
    OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
-               BDW_MOCS_WB << 4 | 1);
+               mocs_wb << 4 | 1);
    /* Dynamic state base address: */
    OUT_RELOC64(brw->batch.bo,
                I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
-               BDW_MOCS_WB << 4 | 1);
+               mocs_wb << 4 | 1);
    /* Indirect object base address: MEDIA_OBJECT data */
+   OUT_BATCH(mocs_wb << 4 | 1);
    OUT_BATCH(0);
-   OUT_BATCH(BDW_MOCS_WB << 4 | 1);
    /* Instruction base address: shader kernels (incl. SIP) */
    OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
-               BDW_MOCS_WB << 4 | 1);
+               mocs_wb << 4 | 1);
 
    /* General state buffer size */
    OUT_BATCH(0xfffff001);
@@ -61,16 +62,21 @@ static void upload_state_base_address(struct brw_context *brw)
    OUT_BATCH(0xfffff001);
    /* Instruction access upper bound */
    OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
+   if (brw->gen >= 9) {
+      OUT_BATCH(1);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+   }
    ADVANCE_BATCH();
 
-   brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
+   brw->ctx.NewDriverState |= BRW_NEW_STATE_BASE_ADDRESS;
 }
 
 const struct brw_tracked_state gen8_state_base_address = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH | BRW_NEW_PROGRAM_CACHE,
-      .cache = 0,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_PROGRAM_CACHE,
    },
    .emit = upload_state_base_address
 };