i965/eu: Take into account the target cache argument in brw_set_dp_read_message.

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_multisample_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
index bfe0d5b610b6d59f7c6a53af2f39756e5de2639c..e36d037d471dee2103374fd16cd5455583e2da12 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -52,13 +52,11 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
    BEGIN_BATCH(9);
    OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
 
-   /* 16x MSAA
-    * XXX: Need to program these.
-    */
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
+   /* 16x MSAA */
+   OUT_BATCH(brw_multisample_positions_16x[0]); /* positions  3,  2,  1,  0 */
+   OUT_BATCH(brw_multisample_positions_16x[1]); /* positions  7,  6,  5,  4 */
+   OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10,  9,  8 */
+   OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */
 
    /* 8x MSAA */
    OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */
@@ -76,20 +74,16 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
 static void
 upload_multisample_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->ctx;
-
-   /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
-   unsigned num_samples = ctx->DrawBuffer->Visual.samples;
-
-   gen8_emit_3dstate_multisample(brw, num_samples);
+   gen8_emit_3dstate_multisample(brw, brw->num_samples);
    gen6_emit_3dstate_sample_mask(brw, gen6_determine_sample_mask(brw));
 }
 
 const struct brw_tracked_state gen8_multisample_state = {
    .dirty = {
-      .mesa = _NEW_BUFFERS | _NEW_MULTISAMPLE,
-      .brw = BRW_NEW_CONTEXT,
-      .cache = 0
+      .mesa = _NEW_MULTISAMPLE,
+      .brw = BRW_NEW_BLORP |
+             BRW_NEW_CONTEXT |
+             BRW_NEW_NUM_SAMPLES,
    },
    .emit = upload_multisample_state
 };