i965: Move curb_read_length/total_scratch to brw_stage_prog_data.

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_ps_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 7d8f9544ee6547642ee32de8f2a8904f92511755..3d3df19916a3bc60cc8e4cfdae920625cf257e5f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -65,8 +65,8 @@ upload_ps_extra(struct brw_context *brw)
    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
 
-   /* _NEW_BUFFERS | _NEW_MULTISAMPLE */
-   bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
+   /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
+   bool multisampled_fbo = brw->num_samples > 1;
    if (multisampled_fbo &&
        _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1)
       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
@@ -85,8 +85,8 @@ upload_ps_extra(struct brw_context *brw)
 
 const struct brw_tracked_state gen8_ps_extra = {
    .dirty = {
-      .mesa  = _NEW_BUFFERS | _NEW_MULTISAMPLE,
-      .brw   = BRW_NEW_CONTEXT | BRW_NEW_FRAGMENT_PROGRAM,
+      .mesa  = _NEW_MULTISAMPLE,
+      .brw   = BRW_NEW_CONTEXT | BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_NUM_SAMPLES,
       .cache = 0,
    },
    .emit = upload_ps_extra,
@@ -134,16 +134,7 @@ static void
 upload_ps_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
-   uint32_t dw3 = 0, dw6 = 0, dw7 = 0;
-
-   /* CACHE_NEW_SAMPLER */
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
-   OUT_BATCH(brw->wm.base.sampler_offset);
-   ADVANCE_BATCH();
-
-   /* CACHE_NEW_WM_PROG */
-   gen8_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
+   uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 
    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
     * incorrect for subspans where some of the pixels are unlit.  We believe
@@ -151,7 +142,6 @@ upload_ps_state(struct brw_context *brw)
     */
    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 
-   /* CACHE_NEW_SAMPLER */
    dw3 |=
       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 
@@ -195,6 +185,8 @@ upload_ps_state(struct brw_context *brw)
    else
       dw6 |= GEN7_PS_POSOFFSET_NONE;
 
+   dw6 |= brw->wm.fast_clear_op;
+
    /* _NEW_MULTISAMPLE
     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
@@ -205,36 +197,38 @@ upload_ps_state(struct brw_context *brw)
       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
    assert(min_invocations_per_fragment >= 1);
 
-   if (brw->wm.prog_data->prog_offset_16) {
+   if (brw->wm.prog_data->prog_offset_16 || brw->wm.prog_data->no_8) {
       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
-      if (min_invocations_per_fragment == 1) {
+      if (!brw->wm.prog_data->no_8 && min_invocations_per_fragment == 1) {
          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
-         dw7 |= (brw->wm.prog_data->first_curbe_grf <<
+         dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
-         dw7 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
+         ksp0 = brw->wm.base.prog_offset;
+         ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
       } else {
-         dw7 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+
+         ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
       }
    } else {
       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
-      dw7 |= (brw->wm.prog_data->first_curbe_grf <<
+      dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+      ksp0 = brw->wm.base.prog_offset;
    }
 
    BEGIN_BATCH(12);
    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
-   if (brw->wm.prog_data->prog_offset_16 && min_invocations_per_fragment > 1)
-      OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
-   else
-      OUT_BATCH(brw->wm.base.prog_offset);
+   OUT_BATCH(ksp0);
    OUT_BATCH(0);
    OUT_BATCH(dw3);
-   if (brw->wm.prog_data->total_scratch) {
+   if (brw->wm.prog_data->base.total_scratch) {
       OUT_RELOC64(brw->wm.base.scratch_bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                  ffs(brw->wm.prog_data->total_scratch) - 11);
+                  ffs(brw->wm.prog_data->base.total_scratch) - 11);
    } else {
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -243,19 +237,17 @@ upload_ps_state(struct brw_context *brw)
    OUT_BATCH(dw7);
    OUT_BATCH(0); /* kernel 1 pointer */
    OUT_BATCH(0);
-   OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
+   OUT_BATCH(ksp2);
    OUT_BATCH(0);
    ADVANCE_BATCH();
 }
 
 const struct brw_tracked_state gen8_ps_state = {
    .dirty = {
-      .mesa  = _NEW_PROGRAM_CONSTANTS | _NEW_MULTISAMPLE,
+      .mesa  = _NEW_MULTISAMPLE,
       .brw   = BRW_NEW_FRAGMENT_PROGRAM |
-               BRW_NEW_PS_BINDING_TABLE |
-               BRW_NEW_BATCH |
-               BRW_NEW_PUSH_CONSTANT_ALLOCATION,
-      .cache = CACHE_NEW_SAMPLER | CACHE_NEW_WM_PROG
+               BRW_NEW_BATCH,
+      .cache = CACHE_NEW_WM_PROG
    },
    .emit = upload_ps_state,
 };