i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c b/src/mesa/drivers/dri/i965/gen8_sol_state.c
index 35a77ac37cf653323e261fc02cfcda4caa079e4d..1f122ec69961d5fc9e3c793f3e49187ec5eedaee 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c
@@ -44,6 +44,7 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
       ctx->TransformFeedback.CurrentObject;
    struct brw_transform_feedback_object *brw_obj =
       (struct brw_transform_feedback_object *) xfb_obj;
+   uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 
    /* Set up the up to 4 output buffers.  These are the ranges defined in the
     * gl_transform_feedback_object.
@@ -79,7 +80,8 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
       OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (8 - 2));
       OUT_BATCH(GEN8_SO_BUFFER_ENABLE | (i << SO_BUFFER_INDEX_SHIFT) |
                 GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE |
-                GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE);
+                GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE |
+                (mocs_wb << 22));
       OUT_RELOC64(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
       OUT_BATCH(xfb_obj->Size[i] / 4 - 1);
       OUT_RELOC64(brw_obj->offset_bo,
@@ -100,14 +102,11 @@ gen8_upload_3dstate_streamout(struct brw_context *brw, bool active,
 {
    struct gl_context *ctx = &brw->ctx;
 
-   /* BRW_NEW_VERTEX_PROGRAM */
-   const struct gl_shader_program *vs_prog =
-      ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX];
    /* BRW_NEW_TRANSFORM_FEEDBACK */
-   const struct gl_transform_feedback_info *linked_xfb_info =
-      &vs_prog->LinkedTransformFeedback;
    struct gl_transform_feedback_object *xfb_obj =
       ctx->TransformFeedback.CurrentObject;
+   const struct gl_transform_feedback_info *linked_xfb_info =
+      &xfb_obj->shader_program->LinkedTransformFeedback;
    uint32_t dw1 = 0, dw2 = 0, dw3 = 0, dw4 = 0;
 
    if (active) {
@@ -169,11 +168,8 @@ const struct brw_tracked_state gen8_sol_state = {
    .dirty = {
       .mesa  = _NEW_LIGHT,
       .brw   = BRW_NEW_BATCH |
-               BRW_NEW_RASTERIZER_DISCARD |
                BRW_NEW_TRANSFORM_FEEDBACK |
-               BRW_NEW_VERTEX_PROGRAM |
                BRW_NEW_VUE_MAP_GEOM_OUT,
-      .cache = 0,
    },
    .emit = upload_sol_state,
 };