i965/vec4: Don't lose the force_writemask_all flag during CSE.

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c b/src/mesa/drivers/dri/i965/gen8_sol_state.c
index ebcdaf8f9c3d950e1f35e9dc5e6ce38ee285ab43..1f122ec69961d5fc9e3c793f3e49187ec5eedaee 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c
@@ -44,6 +44,7 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
       ctx->TransformFeedback.CurrentObject;
    struct brw_transform_feedback_object *brw_obj =
       (struct brw_transform_feedback_object *) xfb_obj;
+   uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 
    /* Set up the up to 4 output buffers.  These are the ranges defined in the
     * gl_transform_feedback_object.
@@ -80,7 +81,7 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
       OUT_BATCH(GEN8_SO_BUFFER_ENABLE | (i << SO_BUFFER_INDEX_SHIFT) |
                 GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE |
                 GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE |
-                (BDW_MOCS_WB << 22));
+                (mocs_wb << 22));
       OUT_RELOC64(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
       OUT_BATCH(xfb_obj->Size[i] / 4 - 1);
       OUT_RELOC64(brw_obj->offset_bo,
@@ -169,7 +170,6 @@ const struct brw_tracked_state gen8_sol_state = {
       .brw   = BRW_NEW_BATCH |
                BRW_NEW_TRANSFORM_FEEDBACK |
                BRW_NEW_VUE_MAP_GEOM_OUT,
-      .cache = 0,
    },
    .emit = upload_sol_state,
 };