i965/skl: Don't use ALL_SLICES_AT_EACH_LOD
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_surface_state.c
index 56c46b0469abe73e3b68a2adf372433ebe0313f2..011c6858b107c8e82e1731b95c8a2ca196143ea5 100644 (file)
@@ -25,6 +25,7 @@
 #include "main/mtypes.h"
 #include "main/samplerobj.h"
 #include "main/texformat.h"
+#include "main/teximage.h"
 #include "program/prog_parameter.h"
 
 #include "intel_mipmap_tree.h"
 #include "brw_defines.h"
 #include "brw_wm.h"
 
+/**
+ * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
+ * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
+ *
+ * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
+ *         0          1          2          3             4            5
+ *         4          5          6          7             0            1
+ *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
+ *
+ * which is simply adding 4 then modding by 8 (or anding with 7).
+ */
+static unsigned
+swizzle_to_scs(unsigned swizzle)
+{
+   return (swizzle + 4) & 7;
+}
+
 static uint32_t
 surface_tiling_mode(uint32_t tiling)
 {
@@ -99,9 +117,9 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
                                unsigned surface_format,
                                unsigned buffer_size,
                                unsigned pitch,
-                               unsigned mocs,
                                bool rw)
 {
+   const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
    uint32_t *surf = allocate_surface_state(brw, out_offset);
 
    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
@@ -111,8 +129,11 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
 
    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
-   surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
-             (pitch - 1);
+   if (surface_format == BRW_SURFACEFORMAT_RAW)
+      surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
+   else
+      surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
+   surf[3] |= (pitch - 1);
    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
@@ -191,7 +212,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
    }
 
-   if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
+   if (_mesa_is_array_texture(tObj->Target) ||
+       tObj->Target == GL_TEXTURE_CUBE_MAP)
       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 
    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
@@ -231,10 +253,10 @@ gen8_update_texture_surface(struct gl_context *ctx,
    const int swizzle =
       unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
    surf[7] |=
-      SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), false), GEN7_SURFACE_SCS_R) |
-      SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), false), GEN7_SURFACE_SCS_G) |
-      SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), false), GEN7_SURFACE_SCS_B) |
-      SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), false), GEN7_SURFACE_SCS_A);
+      SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
+      SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
+      SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
+      SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 
    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 
@@ -257,24 +279,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
                            I915_GEM_DOMAIN_SAMPLER, 0);
 }
 
-static void
-gen8_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo,
-                        uint32_t offset, uint32_t size,
-                        uint32_t *out_offset, bool rw)
-{
-   gen8_emit_buffer_surface_state(brw,
-                                  out_offset,
-                                  bo,
-                                  offset,
-                                  BRW_SURFACEFORMAT_RAW,
-                                  size,
-                                  1,
-                                  0 /* mocs */,
-                                  true /* rw */);
-}
-
 /**
- * Creates a null renderbuffer surface.
+ * Creates a null surface.
  *
  * This is used when the shader doesn't write to any color output.  An FB
  * write to target 0 will still be emitted, because that's how the thread is
@@ -282,23 +288,19 @@ gen8_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo,
  * hardware discard the target 0 color output..
  */
 static void
-gen8_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
+gen8_emit_null_surface_state(struct brw_context *brw,
+                             unsigned width,
+                             unsigned height,
+                             unsigned samples,
+                             uint32_t *out_offset)
 {
-   struct gl_context *ctx = &brw->ctx;
-
-   /* _NEW_BUFFERS */
-   const struct gl_framebuffer *fb = ctx->DrawBuffer;
-   uint32_t surf_index =
-      brw->wm.prog_data->binding_table.render_target_start + unit;
-
-   uint32_t *surf =
-      allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]);
+   uint32_t *surf = allocate_surface_state(brw, out_offset);
 
    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
              GEN8_SURFACE_TILING_Y;
-   surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
+   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 }
 
 /**
@@ -367,7 +369,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
       format = brw->render_target_format[rb_format];
       if (unlikely(!brw->format_supported_as_render_target[rb_format]))
          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-                       __FUNCTION__, _mesa_get_format_name(rb_format));
+                       __func__, _mesa_get_format_name(rb_format));
    }
 
    if (mt->mcs_mt) {
@@ -415,7 +417,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 
-   *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
+   assert(mt->offset % mt->cpp == 0);
+   *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 
    if (aux_mt) {
       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
@@ -432,7 +435,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            brw->wm.base.surf_offset[surf_index] + 8 * 4,
                            mt->bo,
-                           0,
+                           mt->offset,
                            I915_GEM_DOMAIN_RENDER,
                            I915_GEM_DOMAIN_RENDER);
 }
@@ -442,8 +445,6 @@ gen8_init_vtable_surface_functions(struct brw_context *brw)
 {
    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
-   brw->vtbl.update_null_renderbuffer_surface =
-      gen8_update_null_renderbuffer_surface;
-   brw->vtbl.create_raw_surface = gen8_create_raw_surface;
+   brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 }