i965/gen8: Surface state overriding for stencil

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_surface_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d52b32ecd87840f9a8c2ceef823777ee73b65613..406f68e198764814af22d066b3fe349c45dc52fc 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -284,12 +284,16 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
+   unsigned width = mt->logical_width0;
+   unsigned height = mt->logical_height0;
+   unsigned pitch = mt->pitch;
+   uint32_t tiling = mt->tiling;
    uint32_t format = 0;
    uint32_t surf_type;
    bool is_array = false;
-   int depth = MAX2(rb->Depth, 1);
-   int min_array_element;
-
+   int depth = MAX2(irb->layer_count, 1);
+   const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
+      irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
    GLenum gl_target =
       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 
@@ -298,9 +302,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 
    intel_miptree_used_for_rendering(mt);
 
-   /* Render targets can't use IMS layout. */
-   assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
-
    switch (gl_target) {
    case GL_TEXTURE_CUBE_MAP_ARRAY:
    case GL_TEXTURE_CUBE_MAP:
@@ -308,27 +309,31 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
       is_array = true;
       depth *= 6;
       break;
+   case GL_TEXTURE_3D:
+      depth = MAX2(irb->mt->logical_depth0, 1);
+      /* fallthrough */
    default:
       surf_type = translate_tex_target(gl_target);
       is_array = _mesa_tex_target_is_array(gl_target);
       break;
    }
 
-   if (layered) {
-      min_array_element = 0;
-   } else if (mt->num_samples > 1) {
-      min_array_element = irb->mt_layer / mt->num_samples;
-   } else {
-      min_array_element = irb->mt_layer;
-   }
-
    /* _NEW_BUFFERS */
-   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
-   assert(brw_render_target_supported(brw, rb));
-   format = brw->render_target_format[rb_format];
-   if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
-      _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-                    __FUNCTION__, _mesa_get_format_name(rb_format));
+   /* Render targets can't use IMS layout. Stencil in turn gets configured as
+    * single sampled and indexed manually by the program.
+    */
+   if (mt->format == MESA_FORMAT_S_UINT8) {
+      brw_configure_w_tiled(mt, true, &width, &height, &pitch,
+                            &tiling, &format);
+   } else {
+      assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
+      assert(brw_render_target_supported(brw, rb));
+      mesa_format rb_format = _mesa_get_render_format(ctx,
+                                                      intel_rb_format(irb));
+      format = brw->render_target_format[rb_format];
+      if (unlikely(!brw->format_supported_as_render_target[rb_format]))
+         _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+                       __FUNCTION__, _mesa_get_format_name(rb_format));
    }
 
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
@@ -339,20 +344,22 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              (format << BRW_SURFACE_FORMAT_SHIFT) |
              vertical_alignment(mt) |
              horizontal_alignment(mt) |
-             surface_tiling_mode(mt->tiling);
+             surface_tiling_mode(tiling);
 
    surf[1] = SET_FIELD(BDW_MOCS_WT, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 
-   surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
+   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 
    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
-             (mt->pitch - 1); /* Surface Pitch */
+             (pitch - 1); /* Surface Pitch */
 
-   surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
-             min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
+   surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 
+   if (mt->format != MESA_FORMAT_S_UINT8)
+      surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
    surf[5] = irb->mt_level - irb->mt->first_level;
 
    surf[6] = 0; /* Nothing of relevance. */