#include "intel_tex.h"
#include "intel_fbo.h"
#include "intel_buffer_objects.h"
+#include "intel_image.h"
#include "brw_context.h"
#include "brw_state.h"
}
}
-static uint32_t
-surface_tiling_mode(uint32_t tiling)
+uint32_t
+gen8_surface_tiling_mode(uint32_t tiling)
{
switch (tiling) {
case I915_TILING_X:
}
}
-static unsigned
-vertical_alignment(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- uint32_t surf_type)
+unsigned
+gen8_vertical_alignment(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ uint32_t surf_type)
{
/* On Gen9+ vertical alignment is ignored for 1D surfaces and when
* tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value.
}
}
-static unsigned
-horizontal_alignment(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- uint32_t surf_type)
+unsigned
+gen8_horizontal_alignment(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ uint32_t surf_type)
{
/* On Gen9+ horizontal alignment is ignored when tr_mode is not
* TRMODE_NONE. Set to an arbitrary non-reserved value.
}
}
-static uint32_t *
-allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index)
+uint32_t *
+gen8_allocate_surface_state(struct brw_context *brw,
+ uint32_t *out_offset, int index)
{
int dwords = brw->gen >= 9 ? 16 : 13;
uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
bool rw)
{
const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
+ uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
}
}
-static void
-gen8_emit_fast_clear_color(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
+void
+gen8_emit_fast_clear_color(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
uint32_t *surf)
{
if (brw->gen >= 9) {
surf[7] |= mt->fast_clear_color_value;
}
-static uint32_t
+uint32_t
gen8_get_aux_mode(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- uint32_t surf_type)
+ const struct intel_mipmap_tree *mt)
{
if (mt->mcs_mt == NULL)
return GEN8_SURFACE_AUX_MODE_NONE;
if (brw->gen >= 9 || mt->num_samples == 1)
assert(mt->halign == 16);
+ if (intel_miptree_is_lossless_compressed(brw, mt))
+ return GEN9_SURFACE_AUX_MODE_CCS_E;
+
return GEN8_SURFACE_AUX_MODE_MCS;
}
unsigned min_level, unsigned max_level,
unsigned format,
unsigned swizzle,
- uint32_t *surf_offset,
+ uint32_t *surf_offset, int surf_index,
bool rw, bool for_gather)
{
const unsigned depth = max_layer - min_layer;
struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
unsigned tiling_mode, pitch;
const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
const uint32_t surf_type = translate_tex_target(target);
- uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
+ uint32_t aux_mode = gen8_get_aux_mode(brw, mt);
if (mt->format == MESA_FORMAT_S_UINT8) {
tiling_mode = GEN8_SURFACE_TILING_W;
pitch = 2 * mt->pitch;
} else {
- tiling_mode = surface_tiling_mode(mt->tiling);
+ tiling_mode = gen8_surface_tiling_mode(mt->tiling);
pitch = mt->pitch;
}
- /* The MCS is not uploaded for single-sampled surfaces because the color
- * buffer should always have been resolved before it is used as a texture
- * so there is no need for it.
+ /* Prior to Gen9, MCS is not uploaded for single-sampled surfaces because
+ * the color buffer should always have been resolved before it is used as
+ * a texture so there is no need for it. On Gen9 it will be uploaded when
+ * the surface is losslessly compressed (CCS_E).
*/
- if (mt->num_samples <= 1) {
+ if (mt->num_samples <= 1 && aux_mode != GEN9_SURFACE_AUX_MODE_CCS_E) {
aux_mt = NULL;
aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
}
- uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
+ uint32_t *surf = gen8_allocate_surface_state(brw, surf_offset, surf_index);
surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
format << BRW_SURFACE_FORMAT_SHIFT |
- vertical_alignment(brw, mt, surf_type) |
- horizontal_alignment(brw, mt, surf_type) |
+ gen8_vertical_alignment(brw, mt, surf_type) |
+ gen8_horizontal_alignment(brw, mt, surf_type) |
tiling_mode;
if (surf_type == BRW_SURFACE_CUBE) {
gen8_update_texture_surface(struct gl_context *ctx,
unsigned unit,
uint32_t *surf_offset,
- bool for_gather)
+ bool for_gather,
+ uint32_t plane)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
mt = mt->stencil_mt;
format = BRW_SURFACEFORMAT_R8_UINT;
+ } else if (obj->Target == GL_TEXTURE_EXTERNAL_OES) {
+ if (plane > 0)
+ mt = mt->plane[plane - 1];
+ if (mt == NULL)
+ return;
+
+ format = translate_tex_format(brw, mt->format, sampler->sRGBDecode);
+
}
+ const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
+
gen8_emit_texture_surface_state(brw, mt, obj->Target,
obj->MinLayer, obj->MinLayer + depth,
obj->MinLevel + obj->BaseLevel,
obj->MinLevel + intel_obj->_MaxLevel + 1,
format, swizzle, surf_offset,
- false, for_gather);
+ surf_index, false, for_gather);
}
}
unsigned samples,
uint32_t *out_offset)
{
- uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
+ uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
}
struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
- const uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
+ const uint32_t aux_mode = gen8_get_aux_mode(brw, mt);
- uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
+ uint32_t *surf = gen8_allocate_surface_state(brw, &offset, surf_index);
surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
(is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
(format << BRW_SURFACE_FORMAT_SHIFT) |
- vertical_alignment(brw, mt, surf_type) |
- horizontal_alignment(brw, mt, surf_type) |
- surface_tiling_mode(tiling);
+ gen8_vertical_alignment(brw, mt, surf_type) |
+ gen8_horizontal_alignment(brw, mt, surf_type) |
+ gen8_surface_tiling_mode(tiling);
surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
projects / mesa.git / blobdiff