{
}
-void
-gen8_vec4_generator::mark_surface_used(unsigned surf_index)
-{
- assert(surf_index < BRW_MAX_SURFACES);
-
- prog_data->base.binding_table.size_bytes =
- MAX2(prog_data->base.binding_table.size_bytes, (surf_index + 1) * 4);
-}
-
void
gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst)
{
ir->header_present,
BRW_SAMPLER_SIMD_MODE_SIMD4X2);
- mark_surface_used(surf_index);
+ brw_mark_surface_used(&prog_data->base, surf_index);
}
void
false, /* no header */
false); /* EOT */
- mark_surface_used(surf_index);
+ brw_mark_surface_used(&prog_data->base, surf_index);
}
+void
+gen8_vec4_generator::generate_untyped_atomic(vec4_instruction *ir,
+ struct brw_reg dst,
+ struct brw_reg atomic_op,
+ struct brw_reg surf_index)
+{
+ assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
+ atomic_op.type == BRW_REGISTER_TYPE_UD &&
+ surf_index.file == BRW_IMMEDIATE_VALUE &&
+ surf_index.type == BRW_REGISTER_TYPE_UD);
+ assert((atomic_op.dw1.ud & ~0xf) == 0);
+
+ unsigned msg_control =
+ atomic_op.dw1.ud | /* Atomic Operation Type: BRW_AOP_* */
+ (1 << 5); /* Return data expected */
+
+ gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
+ gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD));
+ gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
+ gen8_set_dp_message(brw, inst, HSW_SFID_DATAPORT_DATA_CACHE_1,
+ surf_index.dw1.ud,
+ HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2,
+ msg_control,
+ ir->mlen,
+ 1,
+ ir->header_present,
+ false);
+
+ brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
+}
+
+
+
+void
+gen8_vec4_generator::generate_untyped_surface_read(vec4_instruction *ir,
+ struct brw_reg dst,
+ struct brw_reg surf_index)
+{
+ assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
+ surf_index.type == BRW_REGISTER_TYPE_UD);
+
+ gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
+ gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD));
+ gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
+ gen8_set_dp_message(brw, inst, HSW_SFID_DATAPORT_DATA_CACHE_1,
+ surf_index.dw1.ud,
+ HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ,
+ 0xe, /* enable only the R channel */
+ ir->mlen,
+ 1,
+ ir->header_present,
+ false);
+
+ brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
+}
+
+
void
gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
struct brw_reg dst,
break;
case SHADER_OPCODE_UNTYPED_ATOMIC:
- assert(!"XXX: Missing Gen8 vec4 support for UNTYPED_ATOMIC");
+ generate_untyped_atomic(ir, dst, src[0], src[1]);
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
- assert(!"XXX: Missing Gen8 vec4 support for UNTYPED_SURFACE_READ");
+ generate_untyped_surface_read(ir, dst, src[0]);
break;
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
}
if (unlikely(debug_flag)) {
- disassemble(stderr, last_native_inst_offset, next_inst_offset);
+ gen8_dump_compile(brw, store, last_native_inst_offset, next_inst_offset, stderr);
}
last_native_inst_offset = next_inst_offset;
* case you're doing that.
*/
if (0 && unlikely(debug_flag)) {
- disassemble(stderr, 0, next_inst_offset);
+ gen8_dump_compile(brw, store, 0, next_inst_offset, stderr);
}
}