i965/fs: Make resolve_source_modifiers consistent with the vec4 version

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 9ac681fb4199753a0e6a83d95c8a520e7dbc177b..28f5adddf14397627097c38cb74d8886ab72b229 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -36,16 +36,13 @@ upload_vs_state(struct brw_context *brw)
    const struct brw_stage_state *stage_state = &brw->vs.base;
    uint32_t floating_point_mode = 0;
 
-   /* CACHE_NEW_VS_PROG */
-   const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
+   /* BRW_NEW_VS_PROG_DATA */
+   const struct brw_vue_prog_data *prog_data = &brw->vs.prog_data->base;
 
-   gen7_upload_constant_state(brw, stage_state, true /* active */,
-                              _3DSTATE_CONSTANT_VS);
+   assert(prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
+          prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
 
-   /* Use ALT floating point mode for ARB vertex programs, because they
-    * require 0^0 == 1.
-    */
-   if (ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL)
+   if (prog_data->base.use_alt_mode)
       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 
    BEGIN_BATCH(9);
@@ -58,22 +55,25 @@ upload_vs_state(struct brw_context *brw)
              ((prog_data->base.binding_table.size_bytes / 4) <<
                GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 
-   if (prog_data->total_scratch) {
+   if (prog_data->base.total_scratch) {
       OUT_RELOC64(stage_state->scratch_bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                  ffs(prog_data->total_scratch) - 11);
+                  ffs(prog_data->base.total_scratch) - 11);
    } else {
       OUT_BATCH(0);
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((prog_data->dispatch_grf_start_reg <<
+   OUT_BATCH((prog_data->base.dispatch_grf_start_reg <<
               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
              (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 
+   uint32_t simd8_enable = prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
+      GEN8_VS_SIMD8_ENABLE : 0;
    OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
              GEN6_VS_STATISTICS_ENABLE |
+             simd8_enable |
              GEN6_VS_ENABLE);
 
    /* _NEW_TRANSFORM */
@@ -84,12 +84,10 @@ upload_vs_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen8_vs_state = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
-      .brw   = BRW_NEW_CONTEXT |
-               BRW_NEW_VERTEX_PROGRAM |
-               BRW_NEW_BATCH |
-               BRW_NEW_PUSH_CONSTANT_ALLOCATION,
-      .cache = CACHE_NEW_VS_PROG
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_CONTEXT |
+               BRW_NEW_VS_PROG_DATA,
    },
    .emit = upload_vs_state,
 };