i965/fs: Make resolve_source_modifiers consistent with the vec4 version

[mesa.git] / src / mesa / drivers / dri / i965 / gen8_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index b7af46617391cefd4d75553b8d3a11e1b40f82c7..28f5adddf14397627097c38cb74d8886ab72b229 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -37,7 +37,10 @@ upload_vs_state(struct brw_context *brw)
    uint32_t floating_point_mode = 0;
 
    /* BRW_NEW_VS_PROG_DATA */
-   const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
+   const struct brw_vue_prog_data *prog_data = &brw->vs.prog_data->base;
+
+   assert(prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
+          prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
 
    if (prog_data->base.use_alt_mode)
       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
@@ -66,8 +69,11 @@ upload_vs_state(struct brw_context *brw)
              (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 
+   uint32_t simd8_enable = prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
+      GEN8_VS_SIMD8_ENABLE : 0;
    OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
              GEN6_VS_STATISTICS_ENABLE |
+             simd8_enable |
              GEN6_VS_ENABLE);
 
    /* _NEW_TRANSFORM */