i965: add support for force_gl_vendor

[mesa.git] / src / mesa / drivers / dri / i965 / genX_blorp_exec.c

diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 808bff0db85e8f19c04f244fdc593d3d64866542..219ac585399dfb22061a01374b194b11a0a51a12 100644 (file)
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -94,6 +94,14 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
 #endif
 }
 
+static uint64_t
+blorp_get_surface_address(struct blorp_batch *blorp_batch,
+                          struct blorp_address address)
+{
+   /* We'll let blorp_surface_reloc write the address. */
+   return 0ull;
+}
+
 #if GEN_GEN >= 7 && GEN_GEN < 10
 static struct blorp_address
 blorp_get_surface_base_address(struct blorp_batch *batch)
@@ -175,7 +183,9 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
        */
       .reloc_flags = RELOC_32BIT,
 
-#if GEN_GEN == 10
+#if GEN_GEN == 11
+      .mocs = ICL_MOCS_WB,
+#elif GEN_GEN == 10
       .mocs = CNL_MOCS_WB,
 #elif GEN_GEN == 9
       .mocs = SKL_MOCS_WB,
@@ -183,24 +193,55 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
       .mocs = BDW_MOCS_WB,
 #elif GEN_GEN == 7
       .mocs = GEN7_MOCS_L3,
+#elif GEN_GEN > 6
+#error "Missing MOCS setting!"
 #endif
    };
 
    return data;
 }
 
-#if GEN_GEN >= 8
-static struct blorp_address
-blorp_get_workaround_page(struct blorp_batch *batch)
+/**
+ * See vf_invalidate_for_vb_48b_transitions in genX_state_upload.c.
+ */
+static void
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+                                           const struct blorp_address *addrs,
+                                           UNUSED uint32_t *sizes,
+                                           unsigned num_vbs)
+{
+#if GEN_GEN >= 8 && GEN_GEN < 11
+   struct brw_context *brw = batch->driver_batch;
+   bool need_invalidate = false;
+
+   for (unsigned i = 0; i < num_vbs; i++) {
+      struct brw_bo *bo = addrs[i].buffer;
+      uint16_t high_bits =
+         bo && (bo->kflags & EXEC_OBJECT_PINNED) ? bo->gtt_offset >> 32u : 0;
+
+      if (high_bits != brw->vb.last_bo_high_bits[i]) {
+         need_invalidate = true;
+         brw->vb.last_bo_high_bits[i] = high_bits;
+      }
+   }
+
+   if (need_invalidate) {
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL);
+   }
+#endif
+}
+
+UNUSED static struct blorp_address
+blorp_get_workaround_address(struct blorp_batch *batch)
 {
    assert(batch->blorp->driver_ctx == batch->driver_batch);
    struct brw_context *brw = batch->driver_batch;
 
    return (struct blorp_address) {
       .buffer = brw->workaround_bo,
+      .offset = brw->workaround_bo_offset,
    };
 }
-#endif
 
 static void
 blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start,
@@ -211,26 +252,32 @@ blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start,
     */
 }
 
+#if GEN_GEN >= 7
+static const struct gen_l3_config *
+blorp_get_l3_config(struct blorp_batch *batch)
+{
+   assert(batch->blorp->driver_ctx == batch->driver_batch);
+   struct brw_context *brw = batch->driver_batch;
+
+   return brw->l3.config;
+}
+#else /* GEN_GEN < 7 */
 static void
 blorp_emit_urb_config(struct blorp_batch *batch,
                       unsigned vs_entry_size,
-                      MAYBE_UNUSED unsigned sf_entry_size)
+                      UNUSED unsigned sf_entry_size)
 {
    assert(batch->blorp->driver_ctx == batch->driver_batch);
    struct brw_context *brw = batch->driver_batch;
 
-#if GEN_GEN >= 7
-   if (brw->urb.vsize >= vs_entry_size)
-      return;
-
-   gen7_upload_urb(brw, vs_entry_size, false, false);
-#elif GEN_GEN == 6
+#if GEN_GEN == 6
    gen6_upload_urb(brw, vs_entry_size, false, 0);
 #else
    /* We calculate it now and emit later. */
    brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size);
 #endif
 }
+#endif
 
 void
 genX(blorp_exec)(struct blorp_batch *batch,
@@ -275,11 +322,13 @@ genX(blorp_exec)(struct blorp_batch *batch,
       brw_cache_flush_for_depth(brw, params->stencil.addr.buffer);
 
    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
+   brw_emit_l3_state(brw);
 
 retry:
    intel_batchbuffer_require_space(brw, 1400);
    brw_require_statebuffer_space(brw, 600);
    intel_batchbuffer_save_state(brw);
+   check_aperture_failed_once |= intel_batchbuffer_saved_state_is_empty(brw);
    brw->batch.no_wrap = true;
 
 #if GEN_GEN == 6
@@ -301,6 +350,12 @@ retry:
    gen8_write_pma_stall_bits(brw, 0);
 #endif
 
+   const unsigned scale = params->fast_clear_op ? UINT_MAX : 1;
+   if (brw->current_hash_scale != scale) {
+      brw_emit_hashing_mode(brw, params->x1 - params->x0,
+                            params->y1 - params->y0, scale);
+   }
+
    blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
@@ -337,6 +392,12 @@ retry:
    brw->no_depth_or_stencil = !params->depth.enabled &&
                               !params->stencil.enabled;
    brw->ib.index_size = -1;
+   brw->urb.vsize = 0;
+   brw->urb.gs_present = false;
+   brw->urb.gsize = 0;
+   brw->urb.tess_present = false;
+   brw->urb.hsize = 0;
+   brw->urb.dsize = 0;
 
    if (params->dst.enabled) {
       brw_render_cache_add_bo(brw, params->dst.addr.buffer,