i965: add support for force_gl_vendor

[mesa.git] / src / mesa / drivers / dri / i965 / hsw_queryobj.c

diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index dd51c08c64eb32d59cbf9bb439ed48e515eca12a..f0eb3fdbbd71477a8a61146a07649b12d4f52f2a 100644 (file)
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -26,8 +26,6 @@
  *
  * Support for query buffer objects (GL_ARB_query_buffer_object) on Haswell+.
  */
-#include "main/imports.h"
-
 #include "brw_context.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
@@ -154,7 +152,7 @@ static void
 shr_gpr0_by_2_bits(struct brw_context *brw)
 {
    shl_gpr0_by_30_bits(brw);
-   brw_load_register_reg(brw, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0));
+   brw_load_register_reg(brw, HSW_CS_GPR(0), HSW_CS_GPR(0) + 4);
    brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
 }
 
@@ -193,36 +191,16 @@ load_overflow_data_to_cs_gprs(struct brw_context *brw,
 {
    int offset = idx * sizeof(uint64_t) * 4;
 
-   brw_load_register_mem64(brw,
-                           HSW_CS_GPR(1),
-                           query->bo,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           offset);
+   brw_load_register_mem64(brw, HSW_CS_GPR(1), query->bo, offset);
 
    offset += sizeof(uint64_t);
-   brw_load_register_mem64(brw,
-                           HSW_CS_GPR(2),
-                           query->bo,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           offset);
+   brw_load_register_mem64(brw, HSW_CS_GPR(2), query->bo, offset);
 
    offset += sizeof(uint64_t);
-   brw_load_register_mem64(brw,
-                           HSW_CS_GPR(3),
-                           query->bo,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           offset);
+   brw_load_register_mem64(brw, HSW_CS_GPR(3), query->bo, offset);
 
    offset += sizeof(uint64_t);
-   brw_load_register_mem64(brw,
-                           HSW_CS_GPR(4),
-                           query->bo,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           I915_GEM_DOMAIN_INSTRUCTION,
-                           offset);
+   brw_load_register_mem64(brw, HSW_CS_GPR(4), query->bo, offset);
 }
 
 /*
@@ -293,6 +271,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
                    GLenum pname, GLenum ptype)
 {
    struct brw_context *brw = brw_context(ctx);
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(query->bo);
    assert(pname != GL_QUERY_TARGET);
@@ -302,8 +281,6 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
       brw_load_register_mem64(brw,
                               HSW_CS_GPR(0),
                               query->bo,
-                              I915_GEM_DOMAIN_INSTRUCTION,
-                              I915_GEM_DOMAIN_INSTRUCTION,
                               2 * sizeof(uint64_t));
       return;
    }
@@ -321,8 +298,6 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
       brw_load_register_mem64(brw,
                               HSW_CS_GPR(0),
                               query->bo,
-                              I915_GEM_DOMAIN_INSTRUCTION,
-                              I915_GEM_DOMAIN_INSTRUCTION,
                               0 * sizeof(uint64_t));
    } else if (query->Base.Target == GL_TRANSFORM_FEEDBACK_STREAM_OVERFLOW_ARB
               || query->Base.Target == GL_TRANSFORM_FEEDBACK_OVERFLOW_ARB) {
@@ -333,14 +308,10 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
       brw_load_register_mem64(brw,
                               HSW_CS_GPR(1),
                               query->bo,
-                              I915_GEM_DOMAIN_INSTRUCTION,
-                              I915_GEM_DOMAIN_INSTRUCTION,
                               0 * sizeof(uint64_t));
       brw_load_register_mem64(brw,
                               HSW_CS_GPR(2),
                               query->bo,
-                              I915_GEM_DOMAIN_INSTRUCTION,
-                              I915_GEM_DOMAIN_INSTRUCTION,
                               1 * sizeof(uint64_t));
 
       BEGIN_BATCH(5);
@@ -366,7 +337,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
        * and correctly emitted the number of pixel shader invocations, but,
        * whomever forgot to undo the multiply by 4.
        */
-      if (brw->gen == 8 || brw->is_haswell)
+      if (devinfo->gen == 8 || devinfo->is_haswell)
          shr_gpr0_by_2_bits(brw);
       break;
    case GL_TIME_ELAPSED:
@@ -393,7 +364,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
  * Store immediate data into the user buffer using the requested size.
  */
 static void
-store_query_result_imm(struct brw_context *brw, drm_bacon_bo *bo,
+store_query_result_imm(struct brw_context *brw, struct brw_bo *bo,
                        uint32_t offset, GLenum ptype, uint64_t imm)
 {
    switch (ptype) {
@@ -411,13 +382,12 @@ store_query_result_imm(struct brw_context *brw, drm_bacon_bo *bo,
 }
 
 static void
-set_predicate(struct brw_context *brw, drm_bacon_bo *query_bo)
+set_predicate(struct brw_context *brw, struct brw_bo *query_bo)
 {
    brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull);
 
    /* Load query availability into SRC0 */
    brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo,
-                           I915_GEM_DOMAIN_INSTRUCTION, 0,
                            2 * sizeof(uint64_t));
 
    /* predicate = !(query_availability == 0); */
@@ -435,13 +405,14 @@ set_predicate(struct brw_context *brw, drm_bacon_bo *query_bo)
  * query has not finished yet.
  */
 static void
-store_query_result_reg(struct brw_context *brw, drm_bacon_bo *bo,
+store_query_result_reg(struct brw_context *brw, struct brw_bo *bo,
                        uint32_t offset, GLenum ptype, uint32_t reg,
                        const bool pipelined)
 {
-   uint32_t cmd_size = brw->gen >= 8 ? 4 : 3;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+   uint32_t cmd_size = devinfo->gen >= 8 ? 4 : 3;
    uint32_t dwords = (ptype == GL_INT || ptype == GL_UNSIGNED_INT) ? 1 : 2;
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    BEGIN_BATCH(dwords * cmd_size);
    for (int i = 0; i < dwords; i++) {
@@ -449,12 +420,10 @@ store_query_result_reg(struct brw_context *brw, drm_bacon_bo *bo,
                 (pipelined ? MI_STORE_REGISTER_MEM_PREDICATE : 0) |
                 (cmd_size - 2));
       OUT_BATCH(reg + 4 * i);
-      if (brw->gen >= 8) {
-         OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
-                     I915_GEM_DOMAIN_INSTRUCTION, offset + 4 * i);
+      if (devinfo->gen >= 8) {
+         OUT_RELOC64(bo, RELOC_WRITE, offset + 4 * i);
       } else {
-         OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION,
-                   I915_GEM_DOMAIN_INSTRUCTION, offset + 4 * i);
+         OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, offset + 4 * i);
       }
    }
    ADVANCE_BATCH();