void
intel_batchbuffer_init(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
intel_batchbuffer_reset(brw);
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
/* We can't just use brw_state_batch to get a chunk of space for
* the gen6 workaround because it involves actually writing to
* the buffer, and the kernel doesn't let us write to the batch.
4096, 4096);
}
- if (!intel->has_llc) {
+ if (!brw->has_llc) {
brw->batch.cpu_map = malloc(BATCH_SZ);
brw->batch.map = brw->batch.cpu_map;
}
static void
intel_batchbuffer_reset(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
if (brw->batch.last_bo != NULL) {
drm_intel_bo_unreference(brw->batch.last_bo);
brw->batch.last_bo = NULL;
brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer",
BATCH_SZ, 4096);
- if (intel->has_llc) {
+ if (brw->has_llc) {
drm_intel_bo_map(brw->batch.bo, true);
brw->batch.map = brw->batch.bo->virtual;
}
static void
do_batch_dump(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
struct drm_intel_decode *decode;
struct intel_batchbuffer *batch = &brw->batch;
int ret;
- decode = drm_intel_decode_context_alloc(intel->intelScreen->deviceID);
+ decode = drm_intel_decode_context_alloc(brw->intelScreen->deviceID);
if (!decode)
return;
static int
do_flush_locked(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
struct intel_batchbuffer *batch = &brw->batch;
int ret = 0;
- if (intel->has_llc) {
+ if (brw->has_llc) {
drm_intel_bo_unmap(batch->bo);
} else {
ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
}
}
- if (!intel->intelScreen->no_hw) {
+ if (!brw->intelScreen->no_hw) {
int flags;
- if (intel->gen < 6 || !batch->is_blit) {
+ if (brw->gen < 6 || !batch->is_blit) {
flags = I915_EXEC_RENDER;
} else {
flags = I915_EXEC_BLT;
_intel_batchbuffer_flush(struct brw_context *brw,
const char *file, int line)
{
- struct intel_context *intel = &brw->intel;
int ret;
if (brw->batch.used == 0)
return 0;
- if (intel->first_post_swapbuffers_batch == NULL) {
- intel->first_post_swapbuffers_batch = brw->batch.bo;
- drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
+ if (brw->first_post_swapbuffers_batch == NULL) {
+ brw->first_post_swapbuffers_batch = brw->batch.bo;
+ drm_intel_bo_reference(brw->first_post_swapbuffers_batch);
}
- if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
- fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
- 4*brw->batch.used);
+ if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
+ int bytes_for_commands = 4 * brw->batch.used;
+ int bytes_for_state = brw->batch.bo->size - brw->batch.state_batch_offset;
+ int total_bytes = bytes_for_commands + bytes_for_state;
+ fprintf(stderr, "%s:%d: Batchbuffer flush with %4db (pkt) + "
+ "%4db (state) = %4db (%0.1f%%)\n", file, line,
+ bytes_for_commands, bytes_for_state,
+ total_bytes,
+ 100.0f * total_bytes / BATCH_SZ);
+ }
brw->batch.reserved_space = 0;
intel_upload_finish(brw);
/* Check that we didn't just wrap our batchbuffer at a bad time. */
- assert(!intel->no_batch_wrap);
+ assert(!brw->no_batch_wrap);
ret = do_flush_locked(brw);
void
intel_emit_depth_stall_flushes(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- assert(intel->gen >= 6 && intel->gen <= 7);
+ assert(brw->gen >= 6 && brw->gen <= 7);
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
}
/**
- * From the BSpec, volume 2a.03: VS Stage Input / State:
- * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
+ * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
+ * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
* stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
* 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
void
gen7_emit_vs_workaround_flush(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- assert(intel->gen == 7);
+ assert(brw->gen == 7);
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
void
intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
if (brw->batch.is_blit) {
BEGIN_BATCH_BLT(4);
OUT_BATCH(MI_FLUSH_DW);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
/* Hardware workaround: SNB B-Spec says:
*
* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache