i965/fs: Add support for translating ir_triop_fma into MAD.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_batchbuffer.c

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index e40fe5224a105950b4d9a33b9e1883da15b6ed9e..56048293ade71225b9856adea734fe283767febb 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -58,10 +58,9 @@ clear_cache(struct brw_context *brw)
 void
 intel_batchbuffer_init(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    intel_batchbuffer_reset(brw);
 
-   if (intel->gen >= 6) {
+   if (brw->gen >= 6) {
       /* We can't just use brw_state_batch to get a chunk of space for
        * the gen6 workaround because it involves actually writing to
        * the buffer, and the kernel doesn't let us write to the batch.
@@ -176,7 +175,6 @@ do_batch_dump(struct brw_context *brw)
 static int
 do_flush_locked(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    struct intel_batchbuffer *batch = &brw->batch;
    int ret = 0;
 
@@ -195,7 +193,7 @@ do_flush_locked(struct brw_context *brw)
    if (!brw->intelScreen->no_hw) {
       int flags;
 
-      if (intel->gen < 6 || !batch->is_blit) {
+      if (brw->gen < 6 || !batch->is_blit) {
         flags = I915_EXEC_RENDER;
       } else {
         flags = I915_EXEC_BLT;
@@ -243,9 +241,16 @@ _intel_batchbuffer_flush(struct brw_context *brw,
       drm_intel_bo_reference(brw->first_post_swapbuffers_batch);
    }
 
-   if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
-      fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
-             4*brw->batch.used);
+   if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
+      int bytes_for_commands = 4 * brw->batch.used;
+      int bytes_for_state = brw->batch.bo->size - brw->batch.state_batch_offset;
+      int total_bytes = bytes_for_commands + bytes_for_state;
+      fprintf(stderr, "%s:%d: Batchbuffer flush with %4db (pkt) + "
+              "%4db (state) = %4db (%0.1f%%)\n", file, line,
+              bytes_for_commands, bytes_for_state,
+              total_bytes,
+              100.0f * total_bytes / BATCH_SZ);
+   }
 
    brw->batch.reserved_space = 0;
 
@@ -396,8 +401,7 @@ emit:
 void
 intel_emit_depth_stall_flushes(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   assert(intel->gen >= 6 && intel->gen <= 7);
+   assert(brw->gen >= 6 && brw->gen <= 7);
 
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
@@ -422,8 +426,8 @@ intel_emit_depth_stall_flushes(struct brw_context *brw)
 }
 
 /**
- * From the BSpec, volume 2a.03: VS Stage Input / State:
- * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
+ * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
+ * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
  *  stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
  *  3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
  *  3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL needs
@@ -432,8 +436,7 @@ intel_emit_depth_stall_flushes(struct brw_context *brw)
 void
 gen7_emit_vs_workaround_flush(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   assert(intel->gen == 7);
+   assert(brw->gen == 7);
 
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
@@ -515,8 +518,7 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
 void
 intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   if (intel->gen >= 6) {
+   if (brw->gen >= 6) {
       if (brw->batch.is_blit) {
         BEGIN_BATCH_BLT(4);
         OUT_BATCH(MI_FLUSH_DW);
@@ -525,7 +527,7 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
         OUT_BATCH(0);
         ADVANCE_BATCH();
       } else {
-        if (intel->gen == 6) {
+        if (brw->gen == 6) {
            /* Hardware workaround: SNB B-Spec says:
             *
             * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache