i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks

[mesa.git] / src / mesa / drivers / dri / i965 / intel_batchbuffer.h

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 9d5e8ce7e9c7f3714c43940fafc45c114b75dd67..2783ba3c0fbeea7fe312da6f94b006d901c5f419 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -4,7 +4,7 @@
 #include "main/mtypes.h"
 
 #include "brw_context.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -39,7 +39,7 @@ extern "C" {
 struct intel_batchbuffer;
 
 void intel_batchbuffer_init(struct intel_batchbuffer *batch,
-                            drm_intel_bufmgr *bufmgr,
+                            struct brw_bufmgr *bufmgr,
                             bool has_llc);
 void intel_batchbuffer_free(struct intel_batchbuffer *batch);
 void intel_batchbuffer_save_state(struct brw_context *brw);
@@ -65,12 +65,29 @@ void intel_batchbuffer_data(struct brw_context *brw,
                             const void *data, GLuint bytes,
                             enum brw_gpu_ring ring);
 
-uint64_t intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
-                                 drm_intel_bo *buffer,
-                                 uint32_t offset,
-                                 uint32_t read_domains,
-                                 uint32_t write_domain,
-                                 uint32_t delta);
+bool brw_batch_has_aperture_space(struct brw_context *brw,
+                                  unsigned extra_space_in_bytes);
+
+bool brw_batch_references(struct intel_batchbuffer *batch, struct brw_bo *bo);
+
+uint64_t brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t batch_offset,
+                        struct brw_bo *target, uint32_t target_offset,
+                        uint32_t read_domains, uint32_t write_domain);
+
+static inline uint32_t
+brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
+                 uint32_t prog_offset)
+{
+   if (brw->gen >= 5) {
+      /* Using state base address. */
+      return prog_offset;
+   }
+
+   brw_emit_reloc(&brw->batch, state_offset, brw->cache.bo, prog_offset,
+                  I915_GEM_DOMAIN_INSTRUCTION, 0);
+
+   return brw->cache.bo->offset64 + prog_offset;
+}
 
 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
 
@@ -159,8 +176,8 @@ intel_batchbuffer_advance(struct brw_context *brw)
 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {          \
    uint32_t __offset = (__map - brw->batch.map) * 4;                    \
    uint32_t reloc =                                                     \
-      intel_batchbuffer_reloc(&brw->batch, (buf), __offset,             \
-                              (read_domains), (write_domain), (delta)); \
+      brw_emit_reloc(&brw->batch, __offset, (buf), (delta),             \
+                     (read_domains), (write_domain));                   \
    OUT_BATCH(reloc);                                                    \
 } while (0)
 
@@ -168,8 +185,8 @@ intel_batchbuffer_advance(struct brw_context *brw)
 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do {        \
    uint32_t __offset = (__map - brw->batch.map) * 4;                    \
    uint64_t reloc64 =                                                   \
-      intel_batchbuffer_reloc(&brw->batch, (buf), __offset,             \
-                              (read_domains), (write_domain), (delta)); \
+      brw_emit_reloc(&brw->batch, __offset, (buf), (delta),             \
+                     (read_domains), (write_domain));                   \
    OUT_BATCH(reloc64);                                                  \
    OUT_BATCH(reloc64 >> 32);                                            \
 } while (0)