#define FILE_DEBUG_FLAG DEBUG_BLIT
-#define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
-({ \
- switch (tiling) { \
- case I915_TILING_X: \
- CMD |= type ## _TILED_X; \
- break; \
- case I915_TILING_Y: \
- if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
- CMD |= type ## _TILED_64K; \
- else \
- CMD |= type ## _TILED_Y; \
- break; \
- default: \
- unreachable("not reached"); \
- } \
-})
-
static void
intel_miptree_set_alpha_to_one(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t *y_offset_el)
{
enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
- isl_tiling_get_intratile_offset_el(&brw->isl_dev,
- tiling, mt->cpp, mt->pitch,
+ isl_tiling_get_intratile_offset_el(tiling, mt->cpp * 8, mt->pitch,
total_x_offset_el, total_y_offset_el,
base_address_offset,
x_offset_el, y_offset_el);
* represented per scan line’s worth of graphics data depends on the
* color depth.
*
- * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
- * 16-bit integer to represent buffer pitch, so it can only handle buffer
- * pitches < 32k. However, the pitch is measured in bytes for linear buffers
- * and dwords for tiled buffers.
- *
- * As a result of these two limitations, we can only use the blitter to do
- * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
+ * The blitter's pitch is a signed 16-bit integer, but measured in bytes
+ * for linear surfaces and DWords for tiled surfaces. So the maximum
+ * pitch is 32k linear and 128k tiled.
*/
if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
perf_debug("Falling back due to >= 32k/128k pitch\n");
reverse ? -src_mt->pitch : src_mt->pitch,
src_mt->bo, src_mt->offset + src_offset,
src_mt->tiling,
- src_mt->tr_mode,
dst_mt->pitch,
dst_mt->bo, dst_mt->offset + dst_offset,
dst_mt->tiling,
- dst_mt->tr_mode,
src_tile_x, src_tile_y,
dst_tile_x, dst_tile_y,
chunk_w, chunk_h,
GLenum logicop)
{
/* The blitter doesn't understand multisampling at all. */
- if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
+ if (src_mt->num_samples > 1 || dst_mt->num_samples > 1)
return false;
/* No sRGB decode or encode is done by the hardware blitter, which is
/* The blitter has no idea about HiZ or fast color clears, so we need to
* resolve the miptrees before we do anything.
*/
- intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
- intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
- intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
- intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
+ intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
+ intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
if (src_flip)
src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
return true;
}
-static bool
-alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
+bool
+intel_miptree_copy(struct brw_context *brw,
+ struct intel_mipmap_tree *src_mt,
+ int src_level, int src_slice,
+ uint32_t src_x, uint32_t src_y,
+ struct intel_mipmap_tree *dst_mt,
+ int dst_level, int dst_slice,
+ uint32_t dst_x, uint32_t dst_y,
+ uint32_t src_width, uint32_t src_height)
{
- /* Tiled buffers must be page-aligned (4K). */
- if (tiling != I915_TILING_NONE)
- return (offset & 4095) == 0;
+ /* The blitter doesn't understand multisampling at all. */
+ if (src_mt->num_samples > 1 || dst_mt->num_samples > 1)
+ return false;
- /* On Gen8+, linear buffers must be cacheline-aligned. */
- if (brw->gen >= 8)
- return (offset & 63) == 0;
+ if (src_mt->format == MESA_FORMAT_S_UINT8)
+ return false;
- return true;
-}
+ /* The blitter has no idea about HiZ or fast color clears, so we need to
+ * resolve the miptrees before we do anything.
+ */
+ intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
+ intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
-static bool
-can_fast_copy_blit(struct brw_context *brw,
- drm_intel_bo *src_buffer,
- int16_t src_x, int16_t src_y,
- uintptr_t src_offset, uint32_t src_pitch,
- uint32_t src_tiling, uint32_t src_tr_mode,
- drm_intel_bo *dst_buffer,
- int16_t dst_x, int16_t dst_y,
- uintptr_t dst_offset, uint32_t dst_pitch,
- uint32_t dst_tiling, uint32_t dst_tr_mode,
- int16_t w, int16_t h, uint32_t cpp,
- GLenum logic_op)
-{
- const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
- const bool src_tiling_none = src_tiling == I915_TILING_NONE;
+ uint32_t src_image_x, src_image_y;
+ intel_miptree_get_image_offset(src_mt, src_level, src_slice,
+ &src_image_x, &src_image_y);
- if (brw->gen < 9)
- return false;
+ if (_mesa_is_format_compressed(src_mt->format)) {
+ GLuint bw, bh;
+ _mesa_get_format_block_size(src_mt->format, &bw, &bh);
- /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
- * FIXME: Based on performance data, remove this condition later to
- * enable for all types of surfaces.
- */
- if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
- dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
- return false;
+ /* Compressed textures need not have dimensions that are a multiple of
+ * the block size. Rectangles in compressed textures do need to be a
+ * multiple of the block size. The one exception is that the right and
+ * bottom edges may be at the right or bottom edge of the miplevel even
+ * if it's not aligned.
+ */
+ assert(src_x % bw == 0);
+ assert(src_y % bh == 0);
+ assert(src_width % bw == 0 ||
+ src_x + src_width == minify(src_mt->logical_width0, src_level));
+ assert(src_height % bh == 0 ||
+ src_y + src_height == minify(src_mt->logical_height0, src_level));
+
+ src_x /= (int)bw;
+ src_y /= (int)bh;
+ src_width = DIV_ROUND_UP(src_width, (int)bw);
+ src_height = DIV_ROUND_UP(src_height, (int)bh);
+ }
+ src_x += src_image_x;
+ src_y += src_image_y;
- if (logic_op != GL_COPY)
- return false;
+ uint32_t dst_image_x, dst_image_y;
+ intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
+ &dst_image_x, &dst_image_y);
- /* The start pixel for Fast Copy blit should be on an OWord boundary. */
- if ((dst_x * cpp | src_x * cpp) & 15)
- return false;
+ if (_mesa_is_format_compressed(dst_mt->format)) {
+ GLuint bw, bh;
+ _mesa_get_format_block_size(dst_mt->format, &bw, &bh);
- /* For all surface types buffers must be cacheline-aligned. */
- if ((dst_offset | src_offset) & 63)
- return false;
+ assert(dst_x % bw == 0);
+ assert(dst_y % bh == 0);
- /* Color depths which are not power of 2 or greater than 128 bits are
- * not supported.
- */
- if (!_mesa_is_pow_two(cpp) || cpp > 16)
- return false;
+ dst_x /= (int)bw;
+ dst_y /= (int)bh;
+ }
+ dst_x += dst_image_x;
+ dst_y += dst_image_y;
- /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
- * of the destination pitch must be zero.
- */
- if ((src_pitch >> 15 & 1) != 0 || (dst_pitch >> 15 & 1) != 0)
- return false;
+ return emit_miptree_blit(brw, src_mt, src_x, src_y,
+ dst_mt, dst_x, dst_y,
+ src_width, src_height, false, GL_COPY);
+}
- /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
- if ((src_tiling_none && src_pitch % 16 != 0) ||
- (dst_tiling_none && dst_pitch % 16 != 0))
- return false;
+static bool
+alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
+{
+ /* Tiled buffers must be page-aligned (4K). */
+ if (tiling != I915_TILING_NONE)
+ return (offset & 4095) == 0;
+
+ /* On Gen8+, linear buffers must be cacheline-aligned. */
+ if (brw->gen >= 8)
+ return (offset & 63) == 0;
return true;
}
static uint32_t
-xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
- uint32_t dst_tiling, uint32_t dst_tr_mode,
- uint32_t cpp, bool use_fast_copy_blit)
+xy_blit_cmd(uint32_t src_tiling, uint32_t dst_tiling, uint32_t cpp)
{
uint32_t CMD = 0;
- if (use_fast_copy_blit) {
- CMD = XY_FAST_COPY_BLT_CMD;
-
- if (dst_tiling != I915_TILING_NONE)
- SET_TILING_XY_FAST_COPY_BLT(dst_tiling, dst_tr_mode, XY_FAST_DST);
+ assert(cpp <= 4);
+ switch (cpp) {
+ case 1:
+ case 2:
+ CMD = XY_SRC_COPY_BLT_CMD;
+ break;
+ case 4:
+ CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
+ break;
+ default:
+ unreachable("not reached");
+ }
- if (src_tiling != I915_TILING_NONE)
- SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
- } else {
- assert(cpp <= 4);
- switch (cpp) {
- case 1:
- case 2:
- CMD = XY_SRC_COPY_BLT_CMD;
- break;
- case 4:
- CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
- break;
- default:
- unreachable("not reached");
- }
+ if (dst_tiling != I915_TILING_NONE)
+ CMD |= XY_DST_TILED;
- if (dst_tiling != I915_TILING_NONE)
- CMD |= XY_DST_TILED;
+ if (src_tiling != I915_TILING_NONE)
+ CMD |= XY_SRC_TILED;
- if (src_tiling != I915_TILING_NONE)
- CMD |= XY_SRC_TILED;
- }
return CMD;
}
bool
intelEmitCopyBlit(struct brw_context *brw,
GLuint cpp,
- GLshort src_pitch,
- drm_intel_bo *src_buffer,
+ int32_t src_pitch,
+ struct brw_bo *src_buffer,
GLuint src_offset,
uint32_t src_tiling,
- uint32_t src_tr_mode,
- GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
+ int32_t dst_pitch,
+ struct brw_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
- uint32_t dst_tr_mode,
GLshort src_x, GLshort src_y,
GLshort dst_x, GLshort dst_y,
GLshort w, GLshort h,
GLenum logic_op)
{
- GLuint CMD, BR13, pass = 0;
+ GLuint CMD, BR13;
int dst_y2 = dst_y + h;
int dst_x2 = dst_x + w;
- drm_intel_bo *aper_array[3];
bool dst_y_tiled = dst_tiling == I915_TILING_Y;
bool src_y_tiled = src_tiling == I915_TILING_Y;
- bool use_fast_copy_blit = false;
uint32_t src_tile_w, src_tile_h;
uint32_t dst_tile_w, dst_tile_h;
if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
return false;
+ const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
+
/* do space check before going any further */
- do {
- aper_array[0] = brw->batch.bo;
- aper_array[1] = dst_buffer;
- aper_array[2] = src_buffer;
-
- if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
- intel_batchbuffer_flush(brw);
- pass++;
- } else
- break;
- } while (pass < 2);
-
- if (pass >= 2)
+ if (!brw_batch_has_aperture_space(brw, bo_sizes))
+ intel_batchbuffer_flush(brw);
+
+ if (!brw_batch_has_aperture_space(brw, bo_sizes))
return false;
unsigned length = brw->gen >= 8 ? 10 : 8;
src_buffer, src_pitch, src_offset, src_x, src_y,
dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
- intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h);
- intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h);
+ intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
+ intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
/* For Tiled surfaces, the pitch has to be a multiple of the Tile width
* (X direction width of the Tile). This is ensured while allocating the
assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
- use_fast_copy_blit = can_fast_copy_blit(brw,
- src_buffer,
- src_x, src_y,
- src_offset, src_pitch,
- src_tiling, src_tr_mode,
- dst_buffer,
- dst_x, dst_y,
- dst_offset, dst_pitch,
- dst_tiling, dst_tr_mode,
- w, h, cpp, logic_op);
- if (!use_fast_copy_blit &&
- (src_tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
- dst_tr_mode != INTEL_MIPTREE_TRMODE_NONE))
- return false;
-
- if (use_fast_copy_blit) {
- assert(logic_op == GL_COPY);
-
- /* When two sequential fast copy blits have different source surfaces,
- * but their destinations refer to the same destination surfaces and
- * therefore destinations overlap it is imperative that a flush be
- * inserted between the two blits.
- *
- * FIXME: Figure out a way to avoid flushing when not required.
- */
- brw_emit_mi_flush(brw);
-
- assert(cpp <= 16);
- BR13 = br13_for_cpp(cpp);
-
- if (src_tr_mode == INTEL_MIPTREE_TRMODE_YF)
- BR13 |= XY_FAST_SRC_TRMODE_YF;
-
- if (dst_tr_mode == INTEL_MIPTREE_TRMODE_YF)
- BR13 |= XY_FAST_DST_TRMODE_YF;
-
- CMD = xy_blit_cmd(src_tiling, src_tr_mode,
- dst_tiling, dst_tr_mode,
- cpp, use_fast_copy_blit);
-
- } else {
- /* For big formats (such as floating point), do the copy using 16 or
- * 32bpp and multiply the coordinates.
- */
- if (cpp > 4) {
- if (cpp % 4 == 2) {
- dst_x *= cpp / 2;
- dst_x2 *= cpp / 2;
- src_x *= cpp / 2;
- cpp = 2;
- } else {
- assert(cpp % 4 == 0);
- dst_x *= cpp / 4;
- dst_x2 *= cpp / 4;
- src_x *= cpp / 4;
- cpp = 4;
- }
+ /* For big formats (such as floating point), do the copy using 16 or
+ * 32bpp and multiply the coordinates.
+ */
+ if (cpp > 4) {
+ if (cpp % 4 == 2) {
+ dst_x *= cpp / 2;
+ dst_x2 *= cpp / 2;
+ src_x *= cpp / 2;
+ cpp = 2;
+ } else {
+ assert(cpp % 4 == 0);
+ dst_x *= cpp / 4;
+ dst_x2 *= cpp / 4;
+ src_x *= cpp / 4;
+ cpp = 4;
}
+ }
- if (!alignment_valid(brw, dst_offset, dst_tiling))
- return false;
- if (!alignment_valid(brw, src_offset, src_tiling))
- return false;
+ if (!alignment_valid(brw, dst_offset, dst_tiling))
+ return false;
+ if (!alignment_valid(brw, src_offset, src_tiling))
+ return false;
- /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
- * the low bits. Offsets must be naturally aligned.
- */
- if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
- dst_pitch % 4 != 0 || dst_offset % cpp != 0)
- return false;
+ /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
+ * the low bits. Offsets must be naturally aligned.
+ */
+ if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
+ dst_pitch % 4 != 0 || dst_offset % cpp != 0)
+ return false;
- assert(cpp <= 4);
- BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
+ assert(cpp <= 4);
+ BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
- CMD = xy_blit_cmd(src_tiling, src_tr_mode,
- dst_tiling, dst_tr_mode,
- cpp, use_fast_copy_blit);
- }
+ CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
/* For tiled source and destination, pitch value should be specified
* as a number of Dwords.
GLubyte *src_bits, GLuint src_size,
GLuint fg_color,
GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
+ struct brw_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
GLshort x, GLshort y,
*/
void
intel_emit_linear_blit(struct brw_context *brw,
- drm_intel_bo *dst_bo,
+ struct brw_bo *dst_bo,
unsigned int dst_offset,
- drm_intel_bo *src_bo,
+ struct brw_bo *src_bo,
unsigned int src_offset,
unsigned int size)
{
ok = intelEmitCopyBlit(brw, 1,
pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
- INTEL_MIPTREE_TRMODE_NONE,
pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
- INTEL_MIPTREE_TRMODE_NONE,
src_x, 0, /* src x/y */
dst_x, 0, /* dst x/y */
MIN2(size, pitch), height, /* w, h */
{
uint32_t BR13, CMD;
int pitch, cpp;
- drm_intel_bo *aper_array[2];
pitch = mt->pitch;
cpp = mt->cpp;
BR13 |= pitch;
/* do space check before going any further */
- aper_array[0] = brw->batch.bo;
- aper_array[1] = mt->bo;
-
- if (drm_intel_bufmgr_check_aperture_space(aper_array,
- ARRAY_SIZE(aper_array)) != 0) {
+ if (!brw_batch_has_aperture_space(brw, mt->bo->size))
intel_batchbuffer_flush(brw);
- }
unsigned length = brw->gen >= 8 ? 7 : 6;
bool dst_y_tiled = mt->tiling == I915_TILING_Y;
projects / mesa.git / blobdiff