intel/blorp: Take a destination swizzle in blorp_blit

[mesa.git] / src / mesa / drivers / dri / i965 / intel_buffer_objects.h

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.h b/src/mesa/drivers/dri/i965/intel_buffer_objects.h
index 49aa3aa53b57cb90b3ea3dfeb482e3b40d09f184..b523edc4f0901bb42eb83d07b36930025b57f5f6 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.h
@@ -1,29 +1,27 @@
-/**************************************************************************
- * 
- * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
+/*
+ * Copyright 2005 VMware, Inc.
  * All Rights Reserved.
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
  * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
+ * distribute, sublicense, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
  * the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * 
- **************************************************************************/
+ */
 
 #ifndef INTEL_BUFFEROBJ_H
 #define INTEL_BUFFEROBJ_H
@@ -42,9 +40,13 @@ struct intel_buffer_object
    struct gl_buffer_object Base;
    drm_intel_bo *buffer;     /* the low-level buffer manager's buffer handle */
 
-   drm_intel_bo *range_map_bo;
-   void *range_map_buffer;
-   unsigned int range_map_offset;
+   drm_intel_bo *range_map_bo[MAP_COUNT];
+
+   /**
+    * Alignment offset from the range_map_bo temporary mapping to the returned
+    * obj->Pointer (caused by GL_ARB_map_buffer_alignment).
+    */
+   unsigned map_extra[MAP_COUNT];
 
    /** @{
     * Tracking for what range of the BO may currently be in use by the GPU.
@@ -86,16 +88,17 @@ drm_intel_bo *intel_bufferobj_buffer(struct brw_context *brw,
                                      uint32_t size);
 
 void intel_upload_data(struct brw_context *brw,
-                      const void *ptr, GLuint size, GLuint align,
-                      drm_intel_bo **return_bo,
-                      GLuint *return_offset);
-
-void *intel_upload_map(struct brw_context *brw,
-                      GLuint size, GLuint align);
-void intel_upload_unmap(struct brw_context *brw,
-                       const void *ptr, GLuint size, GLuint align,
-                       drm_intel_bo **return_bo,
-                       GLuint *return_offset);
+                       const void *data,
+                       uint32_t size,
+                       uint32_t alignment,
+                       drm_intel_bo **out_bo,
+                       uint32_t *out_offset);
+
+void *intel_upload_space(struct brw_context *brw,
+                         uint32_t size,
+                         uint32_t alignment,
+                         drm_intel_bo **out_bo,
+                         uint32_t *out_offset);
 
 void intel_upload_finish(struct brw_context *brw);