i965: Remove redundant Gen3 PCI IDs.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_context.h

diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 20c623d1568160469f9cc179e9865cfcf64fb62c..12f093319299227f50745d0d796d30544cf29459 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -57,12 +57,6 @@ extern "C" {
 #include "tnl_dd/t_dd_vertex.h"
 #undef TAG
 
-#define DV_PF_555  (1<<8)
-#define DV_PF_565  (2<<8)
-#define DV_PF_8888 (3<<8)
-#define DV_PF_4444 (8<<8)
-#define DV_PF_1555 (9<<8)
-
 struct intel_region;
 struct intel_context;
 
@@ -76,8 +70,6 @@ typedef void (*intel_point_func) (struct intel_context *, intelVertex *);
 #define INTEL_WRITE_FULL  0x2
 #define INTEL_READ        0x4
 
-#define INTEL_MAX_FIXUP 64
-
 #ifndef likely
 #ifdef __GNUC__
 #define likely(expr) (__builtin_expect(expr, 1))
@@ -134,30 +126,12 @@ struct intel_context
    struct
    {
       void (*destroy) (struct intel_context * intel);
-      void (*emit_state) (struct intel_context * intel);
       void (*finish_batch) (struct intel_context * intel);
       void (*new_batch) (struct intel_context * intel);
-      void (*emit_invarient_state) (struct intel_context * intel);
-      void (*update_texture_state) (struct intel_context * intel);
-
-      void (*render_start) (struct intel_context * intel);
-      void (*render_prevalidate) (struct intel_context * intel);
-      void (*set_draw_region) (struct intel_context * intel,
-                               struct intel_region * draw_regions[],
-                               struct intel_region * depth_region,
-                              GLuint num_regions);
-      void (*update_draw_buffer)(struct intel_context *intel);
-
-      void (*reduced_primitive_state) (struct intel_context * intel,
-                                       GLenum rprim);
-
-      bool (*check_vertex_size) (struct intel_context * intel,
-                                     GLuint expected);
+
       void (*invalidate_state) (struct intel_context *intel,
                                GLuint new_state);
 
-      void (*assert_not_dirty) (struct intel_context *intel);
-
       void (*debug_batch)(struct intel_context *intel);
       void (*annotate_aub)(struct intel_context *intel);
       bool (*render_target_supported)(struct intel_context *intel,
@@ -167,10 +141,6 @@ struct intel_context
       bool (*is_hiz_depth_format)(struct intel_context *intel,
                                  gl_format format);
 
-      /**
-       * Surface state operations (i965+ only)
-       * \{
-       */
       void (*update_texture_surface)(struct gl_context *ctx,
                                      unsigned unit,
                                      uint32_t *binding_table,
@@ -187,7 +157,6 @@ struct intel_context
                                      uint32_t size,
                                      uint32_t *out_offset,
                                       bool dword_pitch);
-      /** \} */
 
       /**
        * Send the appropriate state packets to configure depth, stencil, and
@@ -235,7 +204,6 @@ struct intel_context
    drm_intel_bo *first_post_swapbuffers_batch;
    bool need_throttle;
    bool no_batch_wrap;
-   bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */
 
    /**
     * Set if we're either a debug context or the INTEL_DEBUG=perf environment
@@ -244,19 +212,6 @@ struct intel_context
     */
    bool perf_debug;
 
-   struct
-   {
-      GLuint id;
-      uint32_t start_ptr; /**< for i8xx */
-      uint32_t primitive;      /**< Current hardware primitive type */
-      void (*flush) (struct intel_context *);
-      drm_intel_bo *vb_bo;
-      uint8_t *vb;
-      unsigned int start_offset; /**< Byte offset of primitive sequence */
-      unsigned int current_offset; /**< Byte offset of next vertex */
-      unsigned int count;      /**< Number of vertices in current primitive */
-   } prim;
-
    struct {
       drm_intel_bo *bo;
       GLuint offset;
@@ -269,15 +224,6 @@ struct intel_context
 
    GLuint stats_wm;
 
-   /* Offsets of fields within the current vertex:
-    */
-   GLuint coloroffset;
-   GLuint specoffset;
-   GLuint wpos_offset;
-
-   struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
-   GLuint vertex_attr_count;
-
    bool hw_stencil;
    bool hw_stipple;
    bool no_rast;
@@ -285,20 +231,7 @@ struct intel_context
    bool always_flush_cache;
    bool disable_throttling;
 
-   /* State for intelvb.c and inteltris.c.
-    */
-   GLuint RenderIndex;
-   GLmatrix ViewportMatrix;
-   GLenum render_primitive;
-   GLenum reduced_primitive; /*< Only gen < 6 */
-   GLuint vertex_size;
-   GLubyte *verts;              /* points to tnl->clipspace.vertex_buf */
-
-   /* Fallback rasterization functions 
-    */
-   intel_point_func draw_point;
-   intel_line_func draw_line;
-   intel_tri_func draw_tri;
+   GLenum reduced_primitive;
 
    /**
     * Set if rendering has occured to the drawable's front buffer.
@@ -368,12 +301,6 @@ S_FIXED(float value, uint32_t frac_bits)
    return value * (1 << frac_bits);
 }
 
-#define INTEL_FIREVERTICES(intel)              \
-do {                                           \
-   if ((intel)->prim.flush)                    \
-      (intel)->prim.flush(intel);              \
-} while (0)
-
 /* ================================================================
  * From linux kernel i386 header files, copes with odd sizes better
  * than COPY_DWORDS would:
@@ -477,20 +404,6 @@ extern int INTEL_DEBUG;
    }                                                            \
 } while (0)
 
-#define PCI_CHIP_845_G                 0x2562
-#define PCI_CHIP_I830_M                        0x3577
-#define PCI_CHIP_I855_GM               0x3582
-#define PCI_CHIP_I865_G                        0x2572
-#define PCI_CHIP_I915_G                        0x2582
-#define PCI_CHIP_I915_GM               0x2592
-#define PCI_CHIP_I945_G                        0x2772
-#define PCI_CHIP_I945_GM               0x27A2
-#define PCI_CHIP_I945_GME              0x27AE
-#define PCI_CHIP_G33_G                 0x29C2
-#define PCI_CHIP_Q35_G                 0x29B2
-#define PCI_CHIP_Q33_G                 0x29D2
-
-
 /* ================================================================
  * intel_context.c:
  */
@@ -506,7 +419,6 @@ extern bool intelInitContext(struct intel_context *intel,
                              unsigned *dri_ctx_error);
 
 extern void intelFinish(struct gl_context * ctx);
-extern void intel_flush_rendering_to_batch(struct gl_context *ctx);
 extern void _intel_flush(struct gl_context * ctx, const char *file, int line);
 
 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
@@ -580,7 +492,6 @@ enum {
 extern int intel_translate_shadow_compare_func(GLenum func);
 extern int intel_translate_compare_func(GLenum func);
 extern int intel_translate_stencil_op(GLenum op);
-extern int intel_translate_blend_factor(GLenum factor);
 extern int intel_translate_logic_op(GLenum opcode);
 
 void intel_update_renderbuffers(__DRIcontext *context,