i965: Move intel_context::perf_debug to brw_context.
[mesa.git] / src / mesa / drivers / dri / i965 / intel_context.h
index 9be7fc8a38c9c24f833d5865b509ec19f2c70443..2713eb852a6855cc7347b45dc4224f2aa5ee5a33 100644 (file)
@@ -113,49 +113,8 @@ struct intel_context
 {
    struct gl_context ctx;  /**< base class, must be first field */
 
-   struct
-   {
-      void (*destroy) (struct intel_context * intel);
-      void (*finish_batch) (struct intel_context * intel);
-      void (*new_batch) (struct intel_context * intel);
-
-      void (*update_texture_surface)(struct gl_context *ctx,
-                                     unsigned unit,
-                                     uint32_t *binding_table,
-                                     unsigned surf_index);
-      void (*update_renderbuffer_surface)(struct brw_context *brw,
-                                         struct gl_renderbuffer *rb,
-                                         bool layered,
-                                         unsigned unit);
-      void (*update_null_renderbuffer_surface)(struct brw_context *brw,
-                                              unsigned unit);
-      void (*create_constant_surface)(struct brw_context *brw,
-                                     drm_intel_bo *bo,
-                                     uint32_t offset,
-                                     uint32_t size,
-                                     uint32_t *out_offset,
-                                      bool dword_pitch);
-
-      /**
-       * Send the appropriate state packets to configure depth, stencil, and
-       * HiZ buffers (i965+ only)
-       */
-      void (*emit_depth_stencil_hiz)(struct brw_context *brw,
-                                     struct intel_mipmap_tree *depth_mt,
-                                     uint32_t depth_offset,
-                                     uint32_t depthbuffer_format,
-                                     uint32_t depth_surface_type,
-                                     struct intel_mipmap_tree *stencil_mt,
-                                     bool hiz, bool separate_stencil,
-                                     uint32_t width, uint32_t height,
-                                     uint32_t tile_x, uint32_t tile_y);
-
-   } vtbl;
-
    GLuint NewGLState;
  
-   dri_bufmgr *bufmgr;
-
    /**
     * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
     */
@@ -170,21 +129,6 @@ struct intel_context
    bool has_llc;
    bool has_swizzling;
 
-   drm_intel_context *hw_ctx;
-
-   struct intel_batchbuffer batch;
-
-   drm_intel_bo *first_post_swapbuffers_batch;
-   bool need_throttle;
-   bool no_batch_wrap;
-
-   /**
-    * Set if we're either a debug context or the INTEL_DEBUG=perf environment
-    * variable is set, this is the flag indicating to do expensive work that
-    * might lead to a perf_debug() call.
-    */
-   bool perf_debug;
-
    struct {
       drm_intel_bo *bo;
       GLuint offset;
@@ -195,48 +139,10 @@ struct intel_context
 
    uint32_t max_gtt_map_object_size;
 
-   GLuint stats_wm;
-
-   bool no_rast;
-   bool always_flush_batch;
-   bool always_flush_cache;
-   bool disable_throttling;
-
-   GLenum reduced_primitive;
-
-   /**
-    * Set if rendering has occured to the drawable's front buffer.
-    *
-    * This is used in the DRI2 case to detect that glFlush should also copy
-    * the contents of the fake front buffer to the real front buffer.
-    */
-   bool front_buffer_dirty;
-
-   /**
-    * Track whether front-buffer rendering is currently enabled
-    *
-    * A separate flag is used to track this in order to support MRT more
-    * easily.
-    */
-   bool is_front_buffer_rendering;
-   /**
-    * Track whether front-buffer is the current read target.
-    *
-    * This is closely associated with is_front_buffer_rendering, but may
-    * be set separately.  The DRI2 fake front buffer must be referenced
-    * either way.
-    */
-   bool is_front_buffer_reading;
-
    int driFd;
 
    __DRIcontext *driContext;
    struct intel_screen *intelScreen;
-
-   /**
-    * Configuration cache
-    */
-   driOptionCache optionCache;
 };
 
 /**
@@ -345,8 +251,8 @@ extern int INTEL_DEBUG;
    static GLuint msg_id = 0;                                    \
    if (unlikely(INTEL_DEBUG & DEBUG_PERF))                      \
       dbg_printf(__VA_ARGS__);                                  \
-   if (intel->perf_debug)                                       \
-      _mesa_gl_debug(&intel->ctx, &msg_id,                      \
+   if (brw->perf_debug)                                         \
+      _mesa_gl_debug(&brw->intel.ctx, &msg_id,                  \
                      MESA_DEBUG_TYPE_PERFORMANCE,               \
                      MESA_DEBUG_SEVERITY_MEDIUM,                \
                      __VA_ARGS__);                              \
@@ -372,7 +278,7 @@ extern int INTEL_DEBUG;
  * intel_context.c:
  */
 
-extern bool intelInitContext(struct intel_context *intel,
+extern bool intelInitContext(struct brw_context *brw,
                              int api,
                              unsigned major_version,
                              unsigned minor_version,
@@ -403,10 +309,10 @@ extern int intel_translate_logic_op(GLenum opcode);
 
 void intel_update_renderbuffers(__DRIcontext *context,
                                __DRIdrawable *drawable);
-void intel_prepare_render(struct intel_context *intel);
+void intel_prepare_render(struct brw_context *brw);
 
 void
-intel_resolve_for_dri2_flush(struct intel_context *intel,
+intel_resolve_for_dri2_flush(struct brw_context *brw,
                              __DRIdrawable *drawable);
 
 extern void