i965: Refactor SIMD16-to-2xSIMD8 checks.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_extensions.c

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 4e6627e8f612d51c79a10edc4c9cf1f54ad7006d..608bfac99958341697abf115e47ce7983db5b0e4 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -46,6 +46,10 @@ can_do_pipelined_register_writes(struct brw_context *brw)
    if (brw->gen >= 8)
       return true;
 
+   static int result = -1;
+   if (result != -1)
+      return result;
+
    /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
     * statistics registers), and we already reset it to zero before using it.
     */
@@ -87,9 +91,12 @@ can_do_pipelined_register_writes(struct brw_context *brw)
 
    /* Check whether the value got written. */
    drm_intel_bo_map(brw->batch.workaround_bo, false);
+   data = brw->batch.workaround_bo->virtual;
    bool success = data[offset] == expected_value;
    drm_intel_bo_unmap(brw->batch.workaround_bo);
 
+   result = success;
+
    return success;
 }
 
@@ -99,6 +106,10 @@ can_write_oacontrol(struct brw_context *brw)
    if (brw->gen < 6 || brw->gen >= 8)
       return false;
 
+   static int result = -1;
+   if (result != -1)
+      return result;
+
    /* Set "Select Context ID" to a particular address (which is likely not a
     * context), but leave all counting disabled.  This should be harmless.
     */
@@ -145,9 +156,12 @@ can_write_oacontrol(struct brw_context *brw)
 
    /* Check whether the value got written. */
    drm_intel_bo_map(brw->batch.workaround_bo, false);
+   data = brw->batch.workaround_bo->virtual;
    bool success = data[offset] == expected_value;
    drm_intel_bo_unmap(brw->batch.workaround_bo);
 
+   result = success;
+
    return success;
 }
 
@@ -184,6 +198,7 @@ intelInitExtensions(struct gl_context *ctx)
    ctx->Extensions.ARB_map_buffer_range = true;
    ctx->Extensions.ARB_occlusion_query = true;
    ctx->Extensions.ARB_occlusion_query2 = true;
+   ctx->Extensions.ARB_pipeline_statistics_query = true;
    ctx->Extensions.ARB_point_sprite = true;
    ctx->Extensions.ARB_seamless_cube_map = true;
    ctx->Extensions.ARB_shader_bit_encoding = true;
@@ -254,8 +269,7 @@ intelInitExtensions(struct gl_context *ctx)
 
       ctx->Extensions.EXT_framebuffer_multisample = true;
       ctx->Extensions.EXT_transform_feedback = true;
-      if (brw->gen < 8)
-         ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
+      ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
       ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
       ctx->Extensions.ARB_draw_buffers_blend = true;
       ctx->Extensions.ARB_ES3_compatibility = true;
@@ -272,6 +286,7 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.ARB_texture_gather = true;
       ctx->Extensions.ARB_conditional_render_inverted = true;
       ctx->Extensions.AMD_vertex_shader_layer = true;
+      ctx->Extensions.EXT_polygon_offset_clamp = true;
 
       /* Test if the kernel has the ioctl. */
       if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0)
@@ -331,4 +346,9 @@ intelInitExtensions(struct gl_context *ctx)
 
    if (brw->gen == 7)
       ctx->Extensions.ARB_gpu_shader5 = true;
+
+   ctx->Extensions.OES_texture_float = true;
+   ctx->Extensions.OES_texture_float_linear = true;
+   ctx->Extensions.OES_texture_half_float = true;
+   ctx->Extensions.OES_texture_half_float_linear = true;
 }