}
DBG("%s: rb %d (%s) mt mapped: (%d, %d) (%dx%d) -> %p/%"PRIdPTR"\n",
- __FUNCTION__, rb->Name, _mesa_get_format_name(rb->Format),
+ __func__, rb->Name, _mesa_get_format_name(rb->Format),
x, y, w, h, map, stride);
*out_map = map;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt;
- DBG("%s: rb %d (%s)\n", __FUNCTION__,
+ DBG("%s: rb %d (%s)\n", __func__,
rb->Name, _mesa_get_format_name(rb->Format));
if (srb->Buffer) {
intel_miptree_release(&irb->mt);
- DBG("%s: %s: %s (%dx%d)\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr(internalFormat),
+ DBG("%s: %s: %s (%dx%d)\n", __func__,
+ _mesa_enum_to_string(internalFormat),
_mesa_get_format_name(rb->Format), width, height);
if (width == 0 || height == 0)
image->height,
1,
image->pitch,
- true /*disable_aux_buffers*/);
+ MIPTREE_LAYOUT_DISABLE_AUX);
if (!irb->mt)
return;
irb->mt_layer = layer_multiplier * layer;
- if (layered) {
- irb->layer_count = image->TexObject->NumLayers ?: mt->level[level].depth / layer_multiplier;
- } else {
+ if (!layered) {
irb->layer_count = 1;
+ } else if (image->TexObject->NumLayers > 0) {
+ irb->layer_count = image->TexObject->NumLayers;
+ } else {
+ irb->layer_count = mt->level[level].depth / layer_multiplier;
}
intel_miptree_reference(&irb->mt, mt);
struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
int i;
- DBG("%s() on fb %p (%s)\n", __FUNCTION__,
+ DBG("%s() on fb %p (%s)\n", __func__,
fb, (fb == ctx->DrawBuffer ? "drawbuffer" :
(fb == ctx->ReadBuffer ? "readbuffer" : "other buffer")));
struct intel_mipmap_tree *new_mt;
int width, height, depth;
+ uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
+ MIPTREE_LAYOUT_ALLOC_ANY_TILED;
+
intel_miptree_get_dimensions_for_image(rb->TexImage, &width, &height, &depth);
new_mt = intel_miptree_create(brw, rb->TexImage->TexObject->Target,
intel_image->base.Base.Level,
intel_image->base.Base.Level,
width, height, depth,
- true,
irb->mt->num_samples,
- INTEL_MIPTREE_TILING_ANY,
- false);
+ layout_flags);
if (intel_miptree_wants_hiz_buffer(brw, new_mt)) {
intel_miptree_alloc_hiz(brw, new_mt);
if (!_mesa_set_search(brw->render_cache, bo))
return;
- intel_batchbuffer_emit_mi_flush(brw);
+ brw_emit_mi_flush(brw);
}
/**