i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks

[mesa.git] / src / mesa / drivers / dri / i965 / intel_fbo.c

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index b59fc1fc7d05ddb261803a8ad912f956b9b2e151..91d75ed9cc5b9cacd0e9b977a3394978cd44065b 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -362,31 +362,11 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
     * buffer's content to the main buffer nor for invalidating the aux buffer's
     * content.
     */
-   irb->mt = intel_miptree_create_for_bo(brw,
-                                         image->bo,
-                                         image->format,
-                                         image->offset,
-                                         image->width,
-                                         image->height,
-                                         1,
-                                         image->pitch,
-                                         MIPTREE_LAYOUT_DISABLE_AUX);
+   irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
+                                                ISL_COLORSPACE_NONE, false);
    if (!irb->mt)
       return;
 
-   /* Adjust the miptree's upper-left coordinate.
-    *
-    * FIXME: Adjusting the miptree's layout outside of
-    * intel_miptree_create_layout() is fragile. Plumb the adjustment through
-    * intel_miptree_create_layout() and brw_tex_layout().
-    */
-   irb->mt->level[0].level_x = image->tile_x;
-   irb->mt->level[0].level_y = image->tile_y;
-   irb->mt->level[0].slice[0].x_offset = image->tile_x;
-   irb->mt->level[0].slice[0].y_offset = image->tile_y;
-   irb->mt->total_width += image->tile_x;
-   irb->mt->total_height += image->tile_y;
-
    rb->InternalFormat = image->internal_format;
    rb->Width = image->width;
    rb->Height = image->height;
@@ -576,12 +556,6 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
 
    intel_renderbuffer_set_draw_offset(irb);
 
-   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
-      intel_miptree_alloc_hiz(brw, mt);
-      if (!mt->hiz_buf)
-        return false;
-   }
-
    return true;
 }