#include <GL/internal/dri_interface.h>
#include "intel_batchbuffer.h"
+#include "intel_image.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
#include "intel_blit.h"
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- enum intel_aux_disable aux_disable)
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
- } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+ } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer, the MCS
* buffer. So fallback to UMS, which is identical to CMS without the
* MCS. */
if (brw->gen < 7)
return false;
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
return false;
return true;
}
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!brw->has_hiz)
+ return false;
+
+ switch (mt->format) {
+ case MESA_FORMAT_Z_FLOAT32:
+ case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+ case MESA_FORMAT_Z24_UNORM_X8_UINT:
+ case MESA_FORMAT_Z24_UNORM_S8_UINT:
+ case MESA_FORMAT_Z_UNORM16:
+ return true;
+ default:
+ return false;
+ }
+}
+
+
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
- INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
- mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format, mt->aux_disable);
+ mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil &&
- intel_miptree_wants_hiz_buffer(brw, mt)))) {
+ (brw->has_separate_stencil && intel_miptree_supports_hiz(brw, mt)))) {
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
return NULL;
}
- if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
return mt;
}
+/**
+ * Choose the aux usage for this miptree. This function must be called fairly
+ * late in the miptree create process after we have a tiling.
+ */
+static void
+intel_miptree_choose_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ intel_miptree_supports_ccs(brw, mt)) {
+ if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ brw->gen >= 9 && !mt->is_scanout &&
+ intel_miptree_supports_ccs_e(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else {
+ mt->aux_usage = ISL_AUX_USAGE_CCS_D;
+ }
+ } else if (intel_miptree_supports_hiz(brw, mt)) {
+ mt->aux_usage = ISL_AUX_USAGE_HIZ;
+ }
+
+ /* We can do fast-clear on all auxiliary surface types that are
+ * allocated through the normal texture creation paths.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_NONE)
+ mt->supports_fast_clear = true;
+}
+
+
/**
* Choose an appropriate uncompressed format for a requested
* compressed format, if unsupported.
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
mt->bo->cache_coherent = false;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ intel_miptree_choose_aux_usage(brw, mt);
+
return mt;
}
}
}
- /* If this miptree is capable of supporting fast color clears, set
- * fast_clear_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs or when compressed single sampled buffer is
- * written by the GPU for the first time.
+ /* Since CCS_E can compress more than just clear color, we create the CCS
+ * for it up-front. For CCS_D which only compresses clears, we create the
+ * CCS on-demand when a clear occurs that wants one.
*/
- if (intel_tiling_supports_ccs(brw, mt->tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
-
- /* On Gen9+ clients are not currently capable of consuming compressed
- * single-sampled buffers. Disabling compression allows us to skip
- * resolves.
- */
- const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
- const bool is_lossless_compressed =
- unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_ccs_e(brw, mt);
-
- if (is_lossless_compressed) {
- intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed);
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
}
}
mt->offset = offset;
mt->tiling = tiling;
+ if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ intel_miptree_choose_aux_usage(brw, mt);
+
+ /* Since CCS_E can compress more than just clear color, we create the
+ * CCS for it up-front. For CCS_D which only compresses clears, we
+ * create the CCS on-demand when a clear occurs that wants one.
+ */
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+ }
+
+ return mt;
+}
+
+static struct intel_mipmap_tree *
+miptree_create_for_planar_image(struct brw_context *brw,
+ __DRIimage *image, GLenum target)
+{
+ struct intel_image_format *f = image->planar_format;
+ struct intel_mipmap_tree *planar_mt;
+
+ for (int i = 0; i < f->nplanes; i++) {
+ const int index = f->planes[i].buffer_index;
+ const uint32_t dri_format = f->planes[i].dri_format;
+ const mesa_format format = driImageFormatToGLFormat(dri_format);
+ const uint32_t width = image->width >> f->planes[i].width_shift;
+ const uint32_t height = image->height >> f->planes[i].height_shift;
+
+ /* Disable creation of the texture's aux buffers because the driver
+ * exposes no EGL API to manage them. That is, there is no API for
+ * resolving the aux buffer's content to the main buffer nor for
+ * invalidating the aux buffer's content.
+ */
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, format,
+ image->offsets[index],
+ width, height, 1,
+ image->strides[index],
+ MIPTREE_LAYOUT_DISABLE_AUX);
+ if (mt == NULL)
+ return NULL;
+
+ mt->target = target;
+ mt->total_width = width;
+ mt->total_height = height;
+
+ if (i == 0)
+ planar_mt = mt;
+ else
+ planar_mt->plane[i - 1] = mt;
+ }
+
+ return planar_mt;
+}
+
+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+ __DRIimage *image, GLenum target)
+{
+ if (image->planar_format && image->planar_format->nplanes > 0)
+ return miptree_create_for_planar_image(brw, image, target);
+
+ mesa_format format = image->format;
+
+ if (!brw->ctx.TextureFormatSupported[format]) {
+ /* The texture storage paths in core Mesa detect if the driver does not
+ * support the user-requested format, and then searches for a
+ * fallback format. The DRIimage code bypasses core Mesa, though. So we
+ * do the fallbacks here for important formats.
+ *
+ * We must support DRM_FOURCC_XBGR8888 textures because the Android
+ * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
+ * the Chrome OS compositor consumes as dma_buf EGLImages.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
+ }
+
+ if (!brw->ctx.TextureFormatSupported[format])
+ return NULL;
+
+ /* Disable creation of the texture's aux buffers because the driver exposes
+ * no EGL API to manage them. That is, there is no API for resolving the aux
+ * buffer's content to the main buffer nor for invalidating the aux buffer's
+ * content.
+ */
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, format,
+ image->offset, image->width, image->height, 1,
+ image->pitch,
+ MIPTREE_LAYOUT_DISABLE_AUX);
+ if (mt == NULL)
+ return NULL;
+
+ mt->target = target;
+ mt->level[0].level_x = image->tile_x;
+ mt->level[0].level_y = image->tile_y;
+ mt->level[0].slice[0].x_offset = image->tile_x;
+ mt->level[0].slice[0].y_offset = image->tile_y;
+ mt->total_width += image->tile_x;
+ mt->total_height += image->tile_y;
+
+ /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
+ * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
+ * trouble resolving back to destination image due to alignment issues.
+ */
+ if (!brw->has_surface_tile_offset) {
+ uint32_t draw_x, draw_y;
+ intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
+
+ if (draw_x != 0 || draw_y != 0) {
+ _mesa_error(&brw->ctx, GL_INVALID_OPERATION, __func__);
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+
return mt;
}
if (!singlesample_mt)
goto fail;
- /* If this miptree is capable of supporting fast color clears, set
- * mcs_state appropriately to ensure that fast clears will occur.
- * Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs.
- */
- if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) &&
- intel_miptree_supports_ccs(intel, singlesample_mt)) {
- singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
- }
-
if (num_samples == 0) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
if (!mt)
goto fail;
- if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
/* Multisampled miptrees are only supported for single level. */
assert(mt->first_level == 0);
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- bool is_ccs_e)
+ struct intel_mipmap_tree *mt)
{
assert(mt->mcs_buf == NULL);
- assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS)));
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mt->aux_usage == ISL_AUX_USAGE_CCS_D);
struct isl_surf temp_main_surf;
struct isl_surf temp_ccs_surf;
* not use the gpu access flag which can cause an unnecessary delay if the
* backing pages happened to be just used by the GPU.
*/
- const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags =
+ mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;
mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
&temp_ccs_surf, alloc_flags, mt);
if (!mt->mcs_buf) {
* used for lossless compression which requires similar initialisation
* as multi-sample compression.
*/
- if (is_ccs_e) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* Hardware sets the auxiliary buffer to all zeroes when it does full
* resolve. Initialize it accordingly in case the first renderer is
* cpu (or other none compression aware party).
return true;
}
-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- if (mt->hiz_buf != NULL)
- return false;
-
- if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
- return false;
-
- switch (mt->format) {
- case MESA_FORMAT_Z_FLOAT32:
- case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
- case MESA_FORMAT_Z24_UNORM_X8_UINT:
- case MESA_FORMAT_Z24_UNORM_S8_UINT:
- case MESA_FORMAT_Z_UNORM16:
- return true;
- default:
- return false;
- }
-}
-
bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
unsigned level, unsigned layer)
{
- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) || !mt->mcs_buf)
+ if (!mt->mcs_buf)
return;
/* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
0, INTEL_REMAINING_LAYERS, false, false);
if (mt->mcs_buf) {
- mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
brw_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
}
if (mt->hiz_buf) {
- mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
intel_miptree_aux_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
free(mt->aux_state);
mt->aux_state = NULL;
}
+
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
}
if (!mt->mcs_buf)
return ISL_AUX_USAGE_NONE;
- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- return ISL_AUX_USAGE_MCS;
- }
-
- if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- return ISL_AUX_USAGE_CCS_E;
- }
-
- if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0)
- return ISL_AUX_USAGE_CCS_D;
-
- unreachable("Invalid MCS miptree");
+ return mt->aux_usage;
}
projects / mesa.git / blobdiff