#include "intel_batchbuffer.h"
#include "intel_chipset.h"
#include "intel_mipmap_tree.h"
-#include "intel_regions.h"
#include "intel_resolve_map.h"
#include "intel_tex.h"
#include "intel_blit.h"
#include "brw_context.h"
#include "main/enums.h"
+#include "main/fbobject.h"
#include "main/formats.h"
#include "main/glformats.h"
#include "main/texcompress_etc.h"
#include "main/teximage.h"
#include "main/streaming-load-memcpy.h"
+#include "x86/common_x86_asm.h"
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
case GL_DEPTH_STENCIL:
return INTEL_MSAA_LAYOUT_IMS;
default:
- /* Disable MCS on Broadwell for now. We can enable it once things
- * are working without it.
- */
- if (brw->gen >= 8) {
- perf_debug("Missing CMS support on Broadwell.\n");
- return INTEL_MSAA_LAYOUT_UMS;
- }
-
/* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
*
* This field must be set to 0 for all SINT MSRTs when all RT channels
* would require converting between CMS and UMS MSAA layouts on the fly,
* which is expensive.
*/
- if (_mesa_get_format_datatype(format) == GL_INT) {
- /* TODO: is this workaround needed for future chipsets? */
- assert(brw->gen == 7);
+ if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
} else {
return INTEL_MSAA_LAYOUT_CMS;
struct intel_mipmap_tree *mt,
unsigned *width_px, unsigned *height)
{
- switch (mt->region->tiling) {
+ switch (mt->tiling) {
default:
- assert(!"Non-MSRT MCS requires X or Y tiling");
+ unreachable("Non-MSRT MCS requires X or Y tiling");
/* In release builds, fall through */
case I915_TILING_Y:
*width_px = 32 / mt->cpp;
struct intel_mipmap_tree *mt)
{
/* MCS support does not exist prior to Gen7 */
- if (brw->gen < 7 || brw->gen >= 8)
+ if (brw->gen < 7)
return false;
/* MCS is only supported for color buffers */
return false;
}
- if (mt->region->tiling != I915_TILING_X &&
- mt->region->tiling != I915_TILING_Y)
+ if (mt->tiling != I915_TILING_X &&
+ mt->tiling != I915_TILING_Y)
return false;
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
return false;
}
+/**
+ * Determine depth format corresponding to a depth+stencil format,
+ * for separate stencil.
+ */
+mesa_format
+intel_depth_format_for_depthstencil_format(mesa_format format) {
+ switch (format) {
+ case MESA_FORMAT_Z24_UNORM_S8_UINT:
+ return MESA_FORMAT_Z24_UNORM_X8_UINT;
+ case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+ return MESA_FORMAT_Z_FLOAT32;
+ default:
+ return format;
+ }
+}
+
+
/**
* @param for_bo Indicates that the caller is
* intel_miptree_create_for_bo(). If true, then do not create
GLuint height0,
GLuint depth0,
bool for_bo,
- GLuint num_samples)
+ GLuint num_samples,
+ bool force_all_slices_at_each_lod)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
- DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__,
+ DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(target),
_mesa_get_format_name(format),
- first_level, last_level, mt);
+ first_level, last_level, depth0, mt);
+
+ if (target == GL_TEXTURE_1D_ARRAY) {
+ /* For a 1D Array texture the OpenGL API will treat the height0
+ * parameter as the number of array slices. For Intel hardware, we treat
+ * the 1D array as a 2D Array with a height of 1.
+ *
+ * So, when we first come through this path to create a 1D Array
+ * texture, height0 stores the number of slices, and depth0 is 1. In
+ * this case, we want to swap height0 and depth0.
+ *
+ * Since some miptrees will be created based on the base miptree, we may
+ * come through this path and see height0 as 1 and depth0 being the
+ * number of slices. In this case we don't need to do the swap.
+ */
+ assert(height0 == 1 || depth0 == 1);
+ if (height0 > 1) {
+ depth0 = height0;
+ height0 = 1;
+ }
+ }
mt->target = target;
mt->format = format;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
+ exec_list_make_empty(&mt->hiz_map);
/* The cpp is bytes per (1, blockheight)-sized block for compressed
* textures. This is why you'll see divides by blockheight all over
/* num_samples should already have been quantized to 0, 1, 2, 4, or
* 8.
*/
- assert(false);
+ unreachable("not reached");
}
} else {
/* Non-interleaved */
}
}
- /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
- * use it elsewhere?
+ /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
+ * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
+ * TODO: can we use it elsewhere?
*/
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
- mt->array_spacing_lod0 = false;
+ mt->array_layout = ALL_LOD_IN_EACH_SLICE;
break;
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
- mt->array_spacing_lod0 = true;
+ mt->array_layout = ALL_SLICES_AT_EACH_LOD;
break;
}
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
(brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
+ const bool force_all_slices_at_each_lod = brw->gen == 6;
mt->stencil_mt = intel_miptree_create(brw,
mt->target,
MESA_FORMAT_S_UINT8,
mt->logical_depth0,
true,
num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ force_all_slices_at_each_lod);
if (!mt->stencil_mt) {
intel_miptree_release(&mt);
return NULL;
/* Fix up the Z miptree format for how we're splitting out separate
* stencil. Gen7 expects there to be no stencil bits in its depth buffer.
*/
- if (mt->format == MESA_FORMAT_Z24_UNORM_S8_UINT) {
- mt->format = MESA_FORMAT_Z24_UNORM_X8_UINT;
- } else if (mt->format == MESA_FORMAT_Z32_FLOAT_S8X24_UINT) {
- mt->format = MESA_FORMAT_Z_FLOAT32;
- mt->cpp = 4;
- } else {
- _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
- _mesa_get_format_name(mt->format));
+ mt->format = intel_depth_format_for_depthstencil_format(mt->format);
+ mt->cpp = 4;
+
+ if (format == mt->format) {
+ _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
+ _mesa_get_format_name(mt->format));
}
}
+ if (force_all_slices_at_each_lod)
+ mt->array_layout = ALL_SLICES_AT_EACH_LOD;
+
brw_miptree_layout(brw, mt);
return mt;
return I915_TILING_Y | I915_TILING_X;
}
+
+/**
+ * Choose an appropriate uncompressed format for a requested
+ * compressed format, if unsupported.
+ */
+mesa_format
+intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
+{
+ /* No need to lower ETC formats on these platforms,
+ * they are supported natively.
+ */
+ if (brw->gen >= 8 || brw->is_baytrail)
+ return format;
+
+ switch (format) {
+ case MESA_FORMAT_ETC1_RGB8:
+ return MESA_FORMAT_R8G8B8X8_UNORM;
+ case MESA_FORMAT_ETC2_RGB8:
+ return MESA_FORMAT_R8G8B8X8_UNORM;
+ case MESA_FORMAT_ETC2_SRGB8:
+ case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
+ case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
+ return MESA_FORMAT_B8G8R8A8_SRGB;
+ case MESA_FORMAT_ETC2_RGBA8_EAC:
+ case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1:
+ return MESA_FORMAT_R8G8B8A8_UNORM;
+ case MESA_FORMAT_ETC2_R11_EAC:
+ return MESA_FORMAT_R_UNORM16;
+ case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
+ return MESA_FORMAT_R_SNORM16;
+ case MESA_FORMAT_ETC2_RG11_EAC:
+ return MESA_FORMAT_R16G16_UNORM;
+ case MESA_FORMAT_ETC2_SIGNED_RG11_EAC:
+ return MESA_FORMAT_R16G16_SNORM;
+ default:
+ /* Non ETC1 / ETC2 format */
+ return format;
+ }
+}
+
+
struct intel_mipmap_tree *
intel_miptree_create(struct brw_context *brw,
GLenum target,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode requested_tiling)
+ enum intel_miptree_tiling_mode requested_tiling,
+ bool force_all_slices_at_each_lod)
{
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
mesa_format etc_format = MESA_FORMAT_NONE;
GLuint total_width, total_height;
- if (brw->gen < 8 && !brw->is_baytrail) {
- switch (format) {
- case MESA_FORMAT_ETC1_RGB8:
- format = MESA_FORMAT_R8G8B8X8_UNORM;
- break;
- case MESA_FORMAT_ETC2_RGB8:
- format = MESA_FORMAT_R8G8B8X8_UNORM;
- break;
- case MESA_FORMAT_ETC2_SRGB8:
- case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
- case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
- format = MESA_FORMAT_B8G8R8A8_SRGB;
- break;
- case MESA_FORMAT_ETC2_RGBA8_EAC:
- case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1:
- format = MESA_FORMAT_R8G8B8A8_UNORM;
- break;
- case MESA_FORMAT_ETC2_R11_EAC:
- format = MESA_FORMAT_R_UNORM16;
- break;
- case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
- format = MESA_FORMAT_R_SNORM16;
- break;
- case MESA_FORMAT_ETC2_RG11_EAC:
- format = MESA_FORMAT_R16G16_UNORM;
- break;
- case MESA_FORMAT_ETC2_SIGNED_RG11_EAC:
- format = MESA_FORMAT_R16G16_SNORM;
- break;
- default:
- /* Non ETC1 / ETC2 format */
- break;
- }
- }
+ format = intel_lower_compressed_format(brw, format);
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
mt = intel_miptree_create_layout(brw, target, format,
first_level, last_level, width0,
height0, depth0,
- false, num_samples);
+ false, num_samples,
+ force_all_slices_at_each_lod);
/*
* pitch == 0 || height == 0 indicates the null texture
*/
uint32_t tiling = intel_miptree_choose_tiling(brw, format, width0,
num_samples, requested_tiling,
mt);
- bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
+ bool y_or_x = false;
+ if (tiling == (I915_TILING_Y | I915_TILING_X)) {
+ y_or_x = true;
+ mt->tiling = I915_TILING_Y;
+ } else {
+ mt->tiling = tiling;
+ }
+
+ unsigned long pitch;
mt->etc_format = etc_format;
- mt->region = intel_region_alloc(brw->intelScreen,
- y_or_x ? I915_TILING_Y : tiling,
- mt->cpp,
- total_width,
- total_height,
- expect_accelerated_upload);
-
- /* If the region is too large to fit in the aperture, we need to use the
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ total_width, total_height, mt->cpp,
+ &mt->tiling, &pitch,
+ (expect_accelerated_upload ?
+ BO_ALLOC_FOR_RENDER : 0));
+ mt->pitch = pitch;
+
+ /* If the BO is too large to fit in the aperture, we need to use the
* BLT engine to support it. The BLT paths can't currently handle Y-tiling,
* so we need to fall back to X.
*/
- if (y_or_x && mt->region->bo->size >= brw->max_gtt_map_object_size) {
+ if (y_or_x && mt->bo->size >= brw->max_gtt_map_object_size) {
perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
mt->total_width, mt->total_height);
- intel_region_release(&mt->region);
-
- mt->region = intel_region_alloc(brw->intelScreen,
- I915_TILING_X,
- mt->cpp,
- total_width,
- total_height,
- expect_accelerated_upload);
+
+ mt->tiling = I915_TILING_X;
+ drm_intel_bo_unreference(mt->bo);
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ total_width, total_height, mt->cpp,
+ &mt->tiling, &pitch,
+ (expect_accelerated_upload ?
+ BO_ALLOC_FOR_RENDER : 0));
+ mt->pitch = pitch;
}
mt->offset = 0;
- if (!mt->region) {
+ if (!mt->bo) {
intel_miptree_release(&mt);
return NULL;
}
uint32_t offset,
uint32_t width,
uint32_t height,
- int pitch,
- uint32_t tiling)
+ int pitch)
{
struct intel_mipmap_tree *mt;
+ uint32_t tiling, swizzle;
- struct intel_region *region = calloc(1, sizeof(*region));
- if (!region)
- return NULL;
+ drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
/* Nothing will be able to use this miptree with the BO if the offset isn't
* aligned.
mt = intel_miptree_create_layout(brw, GL_TEXTURE_2D, format,
0, 0,
width, height, 1,
- true, 0 /* num_samples */);
+ true, 0, false);
if (!mt) {
- free(region);
+ free(mt);
return mt;
}
- region->cpp = mt->cpp;
- region->width = width;
- region->height = height;
- region->pitch = pitch;
- region->refcount = 1;
drm_intel_bo_reference(bo);
- region->bo = bo;
- region->tiling = tiling;
-
- mt->region = region;
+ mt->bo = bo;
+ mt->pitch = pitch;
mt->offset = offset;
+ mt->tiling = tiling;
return mt;
}
/**
- * For a singlesample image buffer, this simply wraps the given region with a miptree.
+ * For a singlesample renderbuffer, this simply wraps the given BO with a
+ * miptree.
*
- * For a multisample image buffer, this wraps the given region with
- * a singlesample miptree, then creates a multisample miptree into which the
- * singlesample miptree is embedded as a child.
+ * For a multisample renderbuffer, this wraps the window system's
+ * (singlesample) BO with a singlesample miptree attached to the
+ * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
+ * that will contain the actual rendering (which is lazily resolved to
+ * irb->singlesample_mt).
*/
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct intel_region *region)
+ drm_intel_bo *bo,
+ uint32_t width, uint32_t height,
+ uint32_t pitch)
{
struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
mesa_format format = rb->Format;
int num_samples = rb->NumSamples;
- intel_miptree_release(&irb->mt);
-
/* Only the front and back buffers, which are color buffers, are allocated
* through the image loader.
*/
_mesa_get_format_base_format(format) == GL_RGBA);
singlesample_mt = intel_miptree_create_for_bo(intel,
- region->bo,
+ bo,
format,
0,
- region->width,
- region->height,
- region->pitch,
- region->tiling);
+ width,
+ height,
+ pitch);
if (!singlesample_mt)
- return;
- singlesample_mt->region->name = region->name;
+ goto fail;
/* If this miptree is capable of supporting fast color clears, set
* mcs_state appropriately to ensure that fast clears will occur.
singlesample_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
if (num_samples == 0) {
+ intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
- return;
- }
- multisample_mt = intel_miptree_create_for_renderbuffer(intel,
- format,
- region->width,
- region->height,
- num_samples);
- if (!multisample_mt) {
- intel_miptree_release(&singlesample_mt);
- return;
+ assert(!irb->singlesample_mt);
+ } else {
+ intel_miptree_release(&irb->singlesample_mt);
+ irb->singlesample_mt = singlesample_mt;
+
+ if (!irb->mt ||
+ irb->mt->logical_width0 != width ||
+ irb->mt->logical_height0 != height) {
+ multisample_mt = intel_miptree_create_for_renderbuffer(intel,
+ format,
+ width,
+ height,
+ num_samples);
+ if (!multisample_mt)
+ goto fail;
+
+ irb->need_downsample = false;
+ intel_miptree_release(&irb->mt);
+ irb->mt = multisample_mt;
+ }
}
+ return;
- irb->need_downsample = false;
- irb->mt = multisample_mt;
- irb->singlesample_mt = singlesample_mt;
+fail:
+ intel_miptree_release(&irb->singlesample_mt);
+ intel_miptree_release(&irb->mt);
+ return;
}
struct intel_mipmap_tree*
mt = intel_miptree_create(brw, target, format, 0, 0,
width, height, depth, true, num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY, false);
if (!mt)
goto fail;
DBG("%s deleting %p\n", __FUNCTION__, *mt);
- intel_region_release(&((*mt)->region));
+ drm_intel_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->hiz_mt);
intel_miptree_release(&(*mt)->mcs_mt);
* minification. This will also catch images not present in the
* tree, changed targets, etc.
*/
- if (width != minify(mt->logical_width0, level) ||
- height != minify(mt->logical_height0, level) ||
+ if (width != minify(mt->logical_width0, level - mt->first_level) ||
+ height != minify(mt->logical_height0, level - mt->first_level) ||
depth != level_depth) {
return false;
}
}
void
-intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
+intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
GLuint level, GLuint slice,
GLuint *x, GLuint *y)
{
*y = mt->level[level].slice[slice].y_offset;
}
+/**
+ * This function computes masks that may be used to select the bits of the X
+ * and Y coordinates that indicate the offset within a tile. If the BO is
+ * untiled, the masks are set to 0.
+ */
+void
+intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
+ uint32_t *mask_x, uint32_t *mask_y,
+ bool map_stencil_as_y_tiled)
+{
+ int cpp = mt->cpp;
+ uint32_t tiling = mt->tiling;
+
+ if (map_stencil_as_y_tiled)
+ tiling = I915_TILING_Y;
+
+ switch (tiling) {
+ default:
+ unreachable("not reached");
+ case I915_TILING_NONE:
+ *mask_x = *mask_y = 0;
+ break;
+ case I915_TILING_X:
+ *mask_x = 512 / cpp - 1;
+ *mask_y = 7;
+ break;
+ case I915_TILING_Y:
+ *mask_x = 128 / cpp - 1;
+ *mask_y = 31;
+ break;
+ }
+}
+
+/**
+ * Compute the offset (in bytes) from the start of the BO to the given x
+ * and y coordinate. For tiled BOs, caller must ensure that x and y are
+ * multiples of the tile size.
+ */
+uint32_t
+intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
+ uint32_t x, uint32_t y,
+ bool map_stencil_as_y_tiled)
+{
+ int cpp = mt->cpp;
+ uint32_t pitch = mt->pitch;
+ uint32_t tiling = mt->tiling;
+
+ if (map_stencil_as_y_tiled) {
+ tiling = I915_TILING_Y;
+
+ /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
+ * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
+ * the resulting surface is twice the pitch of the original miptree,
+ * since each row in the Y-tiled view corresponds to two rows in the
+ * actual W-tiled surface. So we need to correct the pitch before
+ * computing the offsets.
+ */
+ pitch *= 2;
+ }
+
+ switch (tiling) {
+ default:
+ unreachable("not reached");
+ case I915_TILING_NONE:
+ return y * pitch + x * cpp;
+ case I915_TILING_X:
+ assert((x % (512 / cpp)) == 0);
+ assert((y % 8) == 0);
+ return y * pitch + x / (512 / cpp) * 4096;
+ case I915_TILING_Y:
+ assert((x % (128 / cpp)) == 0);
+ assert((y % 32) == 0);
+ return y * pitch + x / (128 / cpp) * 4096;
+ }
+}
+
/**
* Rendering with tiled buffers requires that the base address of the buffer
* be aligned to a page boundary. For renderbuffers, and sometimes with
* from there.
*/
uint32_t
-intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
+intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
GLuint level, GLuint slice,
uint32_t *tile_x,
uint32_t *tile_y)
{
- struct intel_region *region = mt->region;
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y, false);
+ intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, false);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
*tile_y = y & mask_y;
- return intel_region_get_aligned_offset(region, x & ~mask_x, y & ~mask_y,
- false);
+ return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y, false);
}
static void
{
mesa_format format = src_mt->format;
- uint32_t width = minify(src_mt->physical_width0, level);
- uint32_t height = minify(src_mt->physical_height0, level);
+ uint32_t width = minify(src_mt->physical_width0, level - src_mt->first_level);
+ uint32_t height = minify(src_mt->physical_height0, level - src_mt->first_level);
int slice;
if (face > 0)
DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
_mesa_get_format_name(src_mt->format),
- src_mt, src_x, src_y, src_mt->region->pitch,
+ src_mt, src_x, src_y, src_mt->pitch,
_mesa_get_format_name(dst_mt->format),
- dst_mt, dst_x, dst_y, dst_mt->region->pitch,
+ dst_mt, dst_x, dst_y, dst_mt->pitch,
width, height);
if (!intel_miptree_blit(brw,
*/
mesa_format format;
switch (num_samples) {
+ case 2:
case 4:
/* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
* each sample).
format = MESA_FORMAT_R_UINT32;
break;
default:
- assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
- return false;
+ unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
};
/* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
mt->logical_depth0,
true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_Y);
+ INTEL_MIPTREE_TILING_Y,
+ false);
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
void *data = intel_miptree_map_raw(brw, mt->mcs_mt);
- memset(data, 0xff, mt->mcs_mt->region->bo->size);
+ memset(data, 0xff, mt->mcs_mt->total_height * mt->mcs_mt->pitch);
intel_miptree_unmap_raw(brw, mt->mcs_mt);
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
mt->logical_depth0,
true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_Y);
+ INTEL_MIPTREE_TILING_Y,
+ false);
return mt->mcs_mt;
}
/**
* Helper for intel_miptree_alloc_hiz() that sets
- * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
+ * \c mt->level[level].has_hiz. Return true if and only if
* \c has_hiz was set.
*/
static bool
-intel_miptree_slice_enable_hiz(struct brw_context *brw,
+intel_miptree_level_enable_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- uint32_t level,
- uint32_t layer)
+ uint32_t level)
{
assert(mt->hiz_mt);
* force the proper size alignments.
*/
if (level > 0 && ((width & 7) || (height & 3))) {
+ DBG("mt %p level %d: HiZ DISABLED\n", mt, level);
return false;
}
}
- mt->level[level].slice[layer].has_hiz = true;
+ DBG("mt %p level %d: HiZ enabled\n", mt, level);
+ mt->level[level].has_hiz = true;
return true;
}
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_mt == NULL);
+ const bool force_all_slices_at_each_lod = brw->gen == 6;
mt->hiz_mt = intel_miptree_create(brw,
mt->target,
mt->format,
mt->logical_depth0,
true,
mt->num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ force_all_slices_at_each_lod);
if (!mt->hiz_mt)
return false;
/* Mark that all slices need a HiZ resolve. */
- struct intel_resolve_map *head = &mt->hiz_map;
for (int level = mt->first_level; level <= mt->last_level; ++level) {
- for (int layer = 0; layer < mt->level[level].depth; ++layer) {
- if (!intel_miptree_slice_enable_hiz(brw, mt, level, layer))
- continue;
+ if (!intel_miptree_level_enable_hiz(brw, mt, level))
+ continue;
- head->next = malloc(sizeof(*head->next));
- head->next->prev = head;
- head->next->next = NULL;
- head = head->next;
+ for (int layer = 0; layer < mt->level[level].depth; ++layer) {
+ struct intel_resolve_map *m = malloc(sizeof(struct intel_resolve_map));
+ exec_node_init(&m->link);
+ m->level = level;
+ m->layer = layer;
+ m->need = GEN6_HIZ_OP_HIZ_RESOLVE;
- head->level = level;
- head->layer = layer;
- head->need = GEN6_HIZ_OP_HIZ_RESOLVE;
+ exec_list_push_tail(&mt->hiz_map, &m->link);
}
}
* Does the miptree slice have hiz enabled?
*/
bool
-intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
- uint32_t level,
- uint32_t layer)
+intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level)
{
- intel_miptree_check_level_layer(mt, level, layer);
- return mt->level[level].slice[layer].has_hiz;
+ intel_miptree_check_level_layer(mt, level, 0);
+ return mt->level[level].has_hiz;
}
void
uint32_t level,
uint32_t layer)
{
- if (!intel_miptree_slice_has_hiz(mt, level, layer))
+ if (!intel_miptree_level_has_hiz(mt, level))
return;
intel_resolve_map_set(&mt->hiz_map,
uint32_t level,
uint32_t layer)
{
- if (!intel_miptree_slice_has_hiz(mt, level, layer))
+ if (!intel_miptree_level_has_hiz(mt, level))
return;
intel_resolve_map_set(&mt->hiz_map,
enum gen6_hiz_op need)
{
bool did_resolve = false;
- struct intel_resolve_map *i, *next;
- for (i = mt->hiz_map.next; i; i = next) {
- next = i->next;
- if (i->need != need)
+ foreach_list_typed_safe(struct intel_resolve_map, map, link, &mt->hiz_map) {
+ if (map->need != need)
continue;
- intel_hiz_exec(brw, mt, i->level, i->layer, need);
- intel_resolve_map_remove(i);
+ intel_hiz_exec(brw, mt, map->level, map->layer, need);
+ intel_resolve_map_remove(map);
did_resolve = true;
}
case INTEL_FAST_CLEAR_STATE_CLEAR:
/* Fast color clear resolves only make sense for non-MSAA buffers. */
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE)
- brw_blorp_resolve_color(brw, mt);
+ brw_meta_resolve_color(brw, mt);
break;
}
}
/**
- * Make it possible to share the region backing the given miptree with another
+ * Make it possible to share the BO backing the given miptree with another
* process or another miptree.
*
* Fast color clears are unsafe with shared buffers, so we need to resolve and
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst)
{
- brw_blorp_blit_miptrees(brw,
- src, 0 /* level */, 0 /* layer */,
- dst, 0 /* level */, 0 /* layer */,
- 0, 0,
- src->logical_width0, src->logical_height0,
- 0, 0,
- dst->logical_width0, dst->logical_height0,
- GL_NEAREST, false, false /*mirror x, y*/);
+ if (brw->gen < 8) {
+ brw_blorp_blit_miptrees(brw,
+ src, 0 /* level */, 0 /* layer */, src->format,
+ dst, 0 /* level */, 0 /* layer */, dst->format,
+ 0, 0,
+ src->logical_width0, src->logical_height0,
+ 0, 0,
+ dst->logical_width0, dst->logical_height0,
+ GL_NEAREST, false, false /*mirror x, y*/);
+ } else if (src->format == MESA_FORMAT_S_UINT8) {
+ brw_meta_stencil_updownsample(brw, src, dst);
+ } else {
+ brw_meta_updownsample(brw, src, dst);
+ }
if (src->stencil_mt) {
+ if (brw->gen >= 8) {
+ brw_meta_stencil_updownsample(brw, src->stencil_mt, dst);
+ return;
+ }
+
brw_blorp_blit_miptrees(brw,
src->stencil_mt, 0 /* level */, 0 /* layer */,
+ src->stencil_mt->format,
dst->stencil_mt, 0 /* level */, 0 /* layer */,
+ dst->stencil_mt->format,
0, 0,
src->logical_width0, src->logical_height0,
0, 0,
*/
intel_miptree_resolve_color(brw, mt);
- drm_intel_bo *bo = mt->region->bo;
+ drm_intel_bo *bo = mt->bo;
- intel_batchbuffer_flush(brw);
+ if (drm_intel_bo_references(brw->batch.bo, bo))
+ intel_batchbuffer_flush(brw);
- if (mt->region->tiling != I915_TILING_NONE)
+ if (mt->tiling != I915_TILING_NONE)
brw_bo_map_gtt(brw, bo, "miptree");
else
brw_bo_map(brw, bo, true, "miptree");
intel_miptree_unmap_raw(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- drm_intel_bo_unmap(mt->region->bo);
+ drm_intel_bo_unmap(mt->bo);
}
static void
x += image_x;
y += image_y;
- map->stride = mt->region->pitch;
+ map->stride = mt->pitch;
map->ptr = base + y * map->stride + x * mt->cpp;
}
0, 0,
map->w, map->h, 1,
false, 0,
- INTEL_MIPTREE_TILING_NONE);
+ INTEL_MIPTREE_TILING_NONE,
+ false);
if (!map->mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
goto fail;
}
- map->stride = map->mt->region->pitch;
+ map->stride = map->mt->pitch;
if (!intel_miptree_blit(brw,
mt, level, slice,
intel_miptree_release(&map->mt);
}
-#ifdef __SSE4_1__
/**
* "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
*/
+#if defined(USE_SSE41)
static void
intel_miptree_map_movntdqa(struct brw_context *brw,
struct intel_mipmap_tree *mt,
void *src = intel_miptree_map_raw(brw, mt);
if (!src)
return;
- src += image_y * mt->region->pitch;
- src += image_x * mt->region->cpp;
+ src += image_y * mt->pitch;
+ src += image_x * mt->cpp;
/* Due to the pixel offsets for the particular image being mapped, our
* src pointer may not be 16-byte aligned. However, if the pitch is
* divisible by 16, then the amount by which it's misaligned will remain
* consistent from row to row.
*/
- assert((mt->region->pitch % 16) == 0);
+ assert((mt->pitch % 16) == 0);
const int misalignment = ((uintptr_t) src) & 15;
/* Create an untiled temporary buffer for the mapping. */
map->stride = ALIGN(misalignment + width_bytes, 16);
- map->buffer = malloc(map->stride * map->h);
+ map->buffer = _mesa_align_malloc(map->stride * map->h, 16);
/* Offset the destination so it has the same misalignment as src. */
map->ptr = map->buffer + misalignment;
for (uint32_t y = 0; y < map->h; y++) {
void *dst_ptr = map->ptr + y * map->stride;
- void *src_ptr = src + y * mt->region->pitch;
+ void *src_ptr = src + y * mt->pitch;
_mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes);
}
unsigned int level,
unsigned int slice)
{
- free(map->buffer);
+ _mesa_align_free(map->buffer);
map->buffer = NULL;
map->ptr = NULL;
}
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
+ ptrdiff_t offset = intel_offset_S8(mt->pitch,
x + image_x + map->x,
y + image_y + map->y,
brw->has_swizzling);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
+ ptrdiff_t offset = intel_offset_S8(mt->pitch,
x + map->x,
y + map->y,
brw->has_swizzling);
image_y += map->y;
uint8_t *dst = intel_miptree_map_raw(brw, mt)
- + image_y * mt->region->pitch
- + image_x * mt->region->cpp;
+ + image_y * mt->pitch
+ + image_x * mt->cpp;
if (mt->etc_format == MESA_FORMAT_ETC1_RGB8)
- _mesa_etc1_unpack_rgba8888(dst, mt->region->pitch,
+ _mesa_etc1_unpack_rgba8888(dst, mt->pitch,
map->ptr, map->stride,
map->w, map->h);
else
- _mesa_unpack_etc2_format(dst, mt->region->pitch,
+ _mesa_unpack_etc2_format(dst, mt->pitch,
map->ptr, map->stride,
map->w, map->h, mt->etc_format);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
int map_x = map->x + x, map_y = map->y + y;
- ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch,
map_x + s_image_x,
map_y + s_image_y,
brw->has_swizzling);
ptrdiff_t z_offset = ((map_y + z_image_y) *
- (z_mt->region->pitch / 4) +
+ (z_mt->pitch / 4) +
(map_x + z_image_x));
uint8_t s = s_map[s_offset];
uint32_t z = z_map[z_offset];
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch,
x + s_image_x + map->x,
y + s_image_y + map->y,
brw->has_swizzling);
- ptrdiff_t z_offset = ((y + z_image_y) *
- (z_mt->region->pitch / 4) +
- (x + z_image_x));
+ ptrdiff_t z_offset = ((y + z_image_y + map->y) *
+ (z_mt->pitch / 4) +
+ (x + z_image_x + map->x));
if (map_z32f_x24s8) {
z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
if (image_x >= 32768 || image_y >= 32768)
return false;
- if (mt->region->pitch >= 32768)
+ if (mt->pitch >= 32768)
return false;
return true;
else if (brw->has_llc &&
!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
- (mt->region->tiling == I915_TILING_X ||
- (brw->gen >= 6 && mt->region->tiling == I915_TILING_Y)) &&
+ (mt->tiling == I915_TILING_X ||
+ (brw->gen >= 6 && mt->tiling == I915_TILING_Y)) &&
can_blit_slice(mt, level, slice)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
- } else if (mt->region->tiling != I915_TILING_NONE &&
- mt->region->bo->size >= brw->max_gtt_map_object_size) {
+ } else if (mt->tiling != I915_TILING_NONE &&
+ mt->bo->size >= brw->max_gtt_map_object_size) {
assert(can_blit_slice(mt, level, slice));
intel_miptree_map_blit(brw, mt, map, level, slice);
-#ifdef __SSE4_1__
- } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed) {
+#if defined(USE_SSE41)
+ } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {
intel_miptree_unmap_depthstencil(brw, mt, map, level, slice);
} else if (map->mt) {
intel_miptree_unmap_blit(brw, mt, map, level, slice);
-#ifdef __SSE4_1__
- } else if (map->buffer) {
+#if defined(USE_SSE41)
+ } else if (map->buffer && cpu_has_sse4_1) {
intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);
#endif
} else {
projects / mesa.git / blobdiff