#include <GL/gl.h>
#include <GL/internal/dri_interface.h>
+#include <drm_fourcc.h>
#include "intel_batchbuffer.h"
#include "intel_image.h"
#include "main/texcompress_etc.h"
#include "main/teximage.h"
#include "main/streaming-load-memcpy.h"
+
+#include "util/format_srgb.h"
+
#include "x86/common_x86_asm.h"
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt);
-static bool
-intel_miptree_alloc_aux(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
static bool
intel_miptree_supports_mcs(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
/* MCS compression only applies to multisampled miptrees */
if (mt->surf.samples <= 1)
return false;
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
+ return false;
+
+ /* See isl_surf_get_mcs_surf for details. */
+ if (mt->surf.samples == 16 && mt->surf.logical_level0_px.width > 8192)
return false;
/* In Gen7, IMS layout is only used for depth and stencil buffers. */
* would require converting between CMS and UMS MSAA layouts on the fly,
* which is expensive.
*/
- if (brw->gen == 7 && _mesa_get_format_datatype(mt->format) == GL_INT) {
+ if (devinfo->gen == 7 && _mesa_get_format_datatype(mt->format) == GL_INT) {
return false;
} else {
return true;
intel_tiling_supports_ccs(const struct brw_context *brw,
enum isl_tiling tiling)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
*
*
* Gen9 changes the restriction to Y-tile only.
*/
- if (brw->gen >= 9)
+ if (devinfo->gen >= 9)
return tiling == ISL_TILING_Y0;
- else if (brw->gen >= 7)
+ else if (devinfo->gen >= 7)
return tiling != ISL_TILING_LINEAR;
else
return false;
intel_miptree_supports_ccs(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
/* MCS support does not exist prior to Gen7 */
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
return false;
/* This function applies only to non-multisampled render targets. */
return false;
/* MCS is only supported for color buffers */
- switch (_mesa_get_format_base_format(mt->format)) {
- case GL_DEPTH_COMPONENT:
- case GL_DEPTH_STENCIL:
- case GL_STENCIL_INDEX:
+ if (!_mesa_is_format_color_format(mt->format))
return false;
- }
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
return false;
* surfaces are supported with MCS buffer layout with these alignments in
* the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
*/
- if (brw->gen < 8 && (mip_mapped || arrayed))
+ if (devinfo->gen < 8 && (mip_mapped || arrayed))
+ return false;
+
+ /* The PRM doesn't say this explicitly, but fast-clears don't appear to
+ * work for 3D textures until gen9 where the layout of 3D textures changes
+ * to match 2D array textures.
+ */
+ if (devinfo->gen <= 8 && mt->surf.dim != ISL_SURF_DIM_2D)
return false;
/* There's no point in using an MCS buffer if the surface isn't in a
intel_tiling_supports_hiz(const struct brw_context *brw,
enum isl_tiling tiling)
{
- if (brw->gen < 6)
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (devinfo->gen < 6)
return false;
return tiling == ISL_TILING_Y0;
}
}
+/**
+ * Return true if the format that will be used to access the miptree is
+ * CCS_E-compatible with the miptree's linear/non-sRGB format.
+ *
+ * Why use the linear format? Well, although the miptree may be specified with
+ * an sRGB format, the usage of that color space/format can be toggled. Since
+ * our HW tends to support more linear formats than sRGB ones, we use this
+ * format variant for check for CCS_E compatibility.
+ */
+static bool
+format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
+ const struct intel_mipmap_tree *mt,
+ enum isl_format access_format)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
+ return isl_formats_are_ccs_e_compatible(devinfo, isl_format, access_format);
+}
+
static bool
intel_miptree_supports_ccs_e(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
- if (brw->gen < 9)
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (devinfo->gen < 9)
return false;
/* For now compression is only enabled for integer formats even though
struct intel_mipmap_tree *mt,
mesa_format format)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
if (_mesa_get_format_base_format(format) != GL_DEPTH_STENCIL)
return false;
- if (brw->must_use_separate_stencil)
+ if (devinfo->must_use_separate_stencil)
return true;
return brw->has_separate_stencil &&
mesa_format
intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
/* No need to lower ETC formats on these platforms,
* they are supported natively.
*/
- if (brw->gen >= 8 || brw->is_baytrail)
+ if (devinfo->gen >= 8 || devinfo->is_baytrail)
return format;
switch (format) {
return mt->surf.logical_level0_px.array_len;
}
-static unsigned
+UNUSED static unsigned
get_num_phys_layers(const struct isl_surf *surf, unsigned level)
{
/* In case of physical dimensions one needs to consider also the layout.
need_to_retile_as_x(const struct brw_context *brw, uint64_t size,
enum isl_tiling tiling)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
/* If the BO is too large to fit in the aperture, we need to use the
* BLT engine to support it. Prior to Sandybridge, the BLT paths can't
* handle Y-tiling, so we need to fall back to X.
*/
- if (brw->gen < 6 && size >= brw->max_gtt_map_object_size &&
+ if (devinfo->gen < 6 && size >= brw->max_gtt_map_object_size &&
tiling == ISL_TILING_Y0)
return true;
.array_len = target == GL_TEXTURE_3D ? 1 : depth0,
.samples = num_samples,
.row_pitch = row_pitch,
- .usage = isl_usage_flags,
+ .usage = isl_usage_flags,
.tiling_flags = tiling_flags,
};
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
- /* In case caller doesn't specifically request Y-tiling (needed
- * unconditionally for depth), check for corner cases needing special
- * treatment.
+ /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
+ * on gen7 platforms we also need to create Y-tiled copies of stencil for
+ * texturing since the hardware can't sample from W-tiled surfaces. For
+ * everything else, check for corner cases needing special treatment.
*/
- if (tiling_flags & ~ISL_TILING_Y0_BIT) {
+ bool is_depth_stencil =
+ mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
+ if (!is_depth_stencil) {
if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
mt->surf.tiling, mt->surf.samples)) {
init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
if (!bo) {
mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
mt->surf.size,
+ BRW_MEMZONE_OTHER,
isl_tiling_to_i915_tiling(
mt->surf.tiling),
mt->surf.row_pitch, alloc_flags);
mt->aux_state = NULL;
mt->cpp = isl_format_get_layout(mt->surf.format)->bpb / 8;
mt->compressed = _mesa_is_format_compressed(format);
+ mt->drm_modifier = DRM_FORMAT_MOD_INVALID;
return mt;
mt->surf.samples, ISL_TILING_W_BIT,
ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, 0, NULL);
+ BO_ALLOC_BUSY, 0, NULL);
if (!mt->stencil_mt)
return false;
-
+
mt->stencil_mt->r8stencil_needs_update = true;
return true;
GLuint height0,
GLuint depth0,
GLuint num_samples,
- uint32_t layout_flags)
+ enum intel_miptree_create_flags flags)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
if (format == MESA_FORMAT_S_UINT8)
return make_surface(brw, target, format, first_level, last_level,
width0, height0, depth0, num_samples,
ISL_TILING_W_BIT,
ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER,
+ BO_ALLOC_BUSY,
0,
NULL);
const GLenum base_format = _mesa_get_format_base_format(format);
if ((base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL) &&
- !(layout_flags & MIPTREE_LAYOUT_TILING_NONE)) {
+ !(flags & MIPTREE_CREATE_LINEAR)) {
/* Fix up the Z miptree format for how we're splitting out separate
* stencil. Gen7 expects there to be no stencil bits in its depth buffer.
*/
const mesa_format depth_only_format =
intel_depth_format_for_depthstencil_format(format);
struct intel_mipmap_tree *mt = make_surface(
- brw, target, brw->gen >= 6 ? depth_only_format : format,
+ brw, target, devinfo->gen >= 6 ? depth_only_format : format,
first_level, last_level,
width0, height0, depth0, num_samples, ISL_TILING_Y0_BIT,
ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, 0, NULL);
+ BO_ALLOC_BUSY, 0, NULL);
if (needs_separate_stencil(brw, mt, format) &&
!make_separate_stencil_surface(brw, mt)) {
return NULL;
}
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return mt;
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
- if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
- alloc_flags |= BO_ALLOC_FOR_RENDER;
+ if (flags & MIPTREE_CREATE_BUSY)
+ alloc_flags |= BO_ALLOC_BUSY;
- isl_tiling_flags_t tiling_flags =
- (layout_flags & MIPTREE_LAYOUT_TILING_NONE) ?
+ isl_tiling_flags_t tiling_flags = (flags & MIPTREE_CREATE_LINEAR) ?
ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
/* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
tiling_flags &= ~ISL_TILING_Y0_BIT;
struct intel_mipmap_tree *mt = make_surface(
mt->etc_format = etc_format;
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return mt;
GLuint height0,
GLuint depth0,
GLuint num_samples,
- uint32_t layout_flags)
+ enum intel_miptree_create_flags flags)
{
assert(num_samples > 0);
brw, target, format,
first_level, last_level,
width0, height0, depth0, num_samples,
- layout_flags);
+ flags);
if (!mt)
return NULL;
mt->offset = 0;
- if (!intel_miptree_alloc_aux(brw, mt)) {
+ /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
+ * compress clear color so we wait until an actual fast-clear to allocate
+ * it.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
+ !intel_miptree_alloc_aux(brw, mt)) {
intel_miptree_release(&mt);
return NULL;
}
uint32_t height,
uint32_t depth,
int pitch,
- uint32_t layout_flags)
+ enum isl_tiling tiling,
+ enum intel_miptree_create_flags flags)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct intel_mipmap_tree *mt;
- uint32_t tiling, swizzle;
const GLenum target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
const GLenum base_format = _mesa_get_format_base_format(format);
const mesa_format depth_only_format =
intel_depth_format_for_depthstencil_format(format);
mt = make_surface(brw, target,
- brw->gen >= 6 ? depth_only_format : format,
+ devinfo->gen >= 6 ? depth_only_format : format,
0, 0, width, height, depth, 1, ISL_TILING_Y0_BIT,
ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, pitch, bo);
+ 0, pitch, bo);
if (!mt)
return NULL;
brw_bo_reference(bo);
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return mt;
ISL_TILING_W_BIT,
ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, pitch, bo);
+ 0, pitch, bo);
if (!mt)
return NULL;
return mt;
}
- brw_bo_get_tiling(bo, &tiling, &swizzle);
-
/* Nothing will be able to use this miptree with the BO if the offset isn't
* aligned.
*/
- if (tiling != I915_TILING_NONE)
+ if (tiling != ISL_TILING_LINEAR)
assert(offset % 4096 == 0);
/* miptrees can't handle negative pitch. If you need flipping of images,
/* The BO already has a tiling format and we shouldn't confuse the lower
* layers by making it try to find a tiling format again.
*/
- assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);
+ assert((flags & MIPTREE_CREATE_LINEAR) == 0);
mt = make_surface(brw, target, format,
0, 0, width, height, depth, 1,
- 1lu << isl_tiling_from_i915_tiling(tiling),
+ 1lu << tiling,
ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
0, pitch, bo);
mt->bo = bo;
mt->offset = offset;
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ if (!(flags & MIPTREE_CREATE_NO_AUX)) {
intel_miptree_choose_aux_usage(brw, mt);
- if (!intel_miptree_alloc_aux(brw, mt)) {
+ /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
+ * only compress clear color so we wait until an actual fast-clear to
+ * allocate it.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
+ !intel_miptree_alloc_aux(brw, mt)) {
intel_miptree_release(&mt);
return NULL;
}
static struct intel_mipmap_tree *
miptree_create_for_planar_image(struct brw_context *brw,
- __DRIimage *image, GLenum target)
+ __DRIimage *image, GLenum target,
+ enum isl_tiling tiling)
{
const struct intel_image_format *f = image->planar_format;
struct intel_mipmap_tree *planar_mt = NULL;
image->offsets[index],
width, height, 1,
image->strides[index],
- MIPTREE_LAYOUT_DISABLE_AUX);
+ tiling,
+ MIPTREE_CREATE_NO_AUX);
if (mt == NULL)
return NULL;
planar_mt->plane[i - 1] = mt;
}
+ planar_mt->drm_modifier = image->modifier;
+
return planar_mt;
}
+static bool
+create_ccs_buf_for_image(struct brw_context *brw,
+ __DRIimage *image,
+ struct intel_mipmap_tree *mt,
+ enum isl_aux_state initial_state)
+{
+ struct isl_surf temp_ccs_surf;
+
+ /* CCS is only supported for very simple miptrees */
+ assert(image->aux_offset != 0 && image->aux_pitch != 0);
+ assert(image->tile_x == 0 && image->tile_y == 0);
+ assert(mt->surf.samples == 1);
+ assert(mt->surf.levels == 1);
+ assert(mt->surf.logical_level0_px.depth == 1);
+ assert(mt->surf.logical_level0_px.array_len == 1);
+ assert(mt->first_level == 0);
+ assert(mt->last_level == 0);
+
+ /* We shouldn't already have a CCS */
+ assert(!mt->aux_buf);
+
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &temp_ccs_surf,
+ image->aux_pitch))
+ return false;
+
+ assert(image->aux_offset < image->bo->size);
+ assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+
+ mt->aux_buf = calloc(sizeof(*mt->aux_buf), 1);
+ if (mt->aux_buf == NULL)
+ return false;
+
+ mt->aux_state = create_aux_state_map(mt, initial_state);
+ if (!mt->aux_state) {
+ free(mt->aux_buf);
+ mt->aux_buf = NULL;
+ return false;
+ }
+
+ /* On gen10+ we start using an extra space in the aux buffer to store the
+ * indirect clear color. However, if we imported an image from the window
+ * system with CCS, we don't have the extra space at the end of the aux
+ * buffer. So create a new bo here that will store that clear color.
+ */
+ if (brw->isl_dev.ss.clear_color_state_size > 0) {
+ mt->aux_buf->clear_color_bo =
+ brw_bo_alloc_tiled(brw->bufmgr, "clear_color_bo",
+ brw->isl_dev.ss.clear_color_state_size,
+ BRW_MEMZONE_OTHER, I915_TILING_NONE, 0,
+ BO_ALLOC_ZEROED);
+ if (!mt->aux_buf->clear_color_bo) {
+ free(mt->aux_buf);
+ mt->aux_buf = NULL;
+ return false;
+ }
+ }
+
+ mt->aux_buf->bo = image->bo;
+ brw_bo_reference(image->bo);
+
+ mt->aux_buf->offset = image->aux_offset;
+ mt->aux_buf->surf = temp_ccs_surf;
+
+ return true;
+}
+
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
- enum isl_colorspace colorspace,
+ mesa_format format,
bool is_winsys_image)
{
- if (image->planar_format && image->planar_format->nplanes > 0) {
- assert(colorspace == ISL_COLORSPACE_NONE ||
- colorspace == ISL_COLORSPACE_YUV);
- return miptree_create_for_planar_image(brw, image, target);
- }
+ uint32_t bo_tiling, bo_swizzle;
+ brw_bo_get_tiling(image->bo, &bo_tiling, &bo_swizzle);
- mesa_format format = image->format;
- switch (colorspace) {
- case ISL_COLORSPACE_NONE:
- /* Keep the image format unmodified */
- break;
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
- case ISL_COLORSPACE_LINEAR:
- format =_mesa_get_srgb_format_linear(format);
- break;
+ const enum isl_tiling tiling =
+ mod_info ? mod_info->tiling : isl_tiling_from_i915_tiling(bo_tiling);
- case ISL_COLORSPACE_SRGB:
- format =_mesa_get_linear_format_srgb(format);
- break;
+ if (image->planar_format && image->planar_format->nplanes > 1)
+ return miptree_create_for_planar_image(brw, image, target, tiling);
- default:
- unreachable("Inalid colorspace for non-planar image");
- }
+ if (image->planar_format)
+ assert(image->planar_format->planes[0].dri_format == image->dri_format);
if (!brw->ctx.TextureFormatSupported[format]) {
/* The texture storage paths in core Mesa detect if the driver does not
if (!brw->ctx.TextureFormatSupported[format])
return NULL;
+ enum intel_miptree_create_flags mt_create_flags = 0;
+
/* If this image comes in from a window system, we have different
* requirements than if it comes in via an EGL import operation. Window
* system images can use any form of auxiliary compression we wish because
* they get "flushed" before being handed off to the window system and we
- * have the opportunity to do resolves. Window system buffers also may be
- * used for scanout so we need to flag that appropriately.
+ * have the opportunity to do resolves. Non window-system images, on the
+ * other hand, have no resolve point so we can't have aux without a
+ * modifier.
*/
- const uint32_t mt_layout_flags =
- is_winsys_image ? 0 : MIPTREE_LAYOUT_DISABLE_AUX;
+ if (!is_winsys_image)
+ mt_create_flags |= MIPTREE_CREATE_NO_AUX;
+
+ /* If we have a modifier which specifies aux, don't create one yet */
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE)
+ mt_create_flags |= MIPTREE_CREATE_NO_AUX;
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
image->offset, image->width, image->height, 1,
- image->pitch, mt_layout_flags);
+ image->pitch, tiling, mt_create_flags);
if (mt == NULL)
return NULL;
mt->target = target;
mt->level[0].level_x = image->tile_x;
mt->level[0].level_y = image->tile_y;
+ mt->drm_modifier = image->modifier;
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
* trouble resolving back to destination image due to alignment issues.
*/
- if (!brw->has_surface_tile_offset) {
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ if (!devinfo->has_surface_tile_offset) {
uint32_t draw_x, draw_y;
intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
}
}
- /* If this is a window-system image, then we can no longer assume it's
- * cache-coherent because it may suddenly get scanned out which destroys
- * coherency.
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mt->aux_usage = mod_info->aux_usage;
+ /* If we are a window system buffer, then we can support fast-clears
+ * even if the modifier doesn't support them by doing a partial resolve
+ * as part of the flush operation.
+ */
+ mt->supports_fast_clear =
+ is_winsys_image || mod_info->supports_clear_color;
+
+ /* We don't know the actual state of the surface when we get it but we
+ * can make a pretty good guess based on the modifier. What we do know
+ * for sure is that it isn't in the AUX_INVALID state, so we just assume
+ * a worst case of compression.
+ */
+ enum isl_aux_state initial_state =
+ isl_drm_modifier_get_default_aux_state(image->modifier);
+
+ if (!create_ccs_buf_for_image(brw, image, mt, initial_state)) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+
+ /* Don't assume coherency for imported EGLimages. We don't know what
+ * external clients are going to do with it. They may scan it out.
*/
- if (is_winsys_image)
- image->bo->cache_coherent = false;
+ image->bo->cache_coherent = false;
return mt;
}
struct intel_mipmap_tree *mt;
uint32_t depth = 1;
GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
- const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
mt = intel_miptree_create(brw, target, format, 0, 0,
width, height, depth, num_samples,
- layout_flags);
+ MIPTREE_CREATE_BUSY);
if (!mt)
goto fail;
return;
brw_bo_unreference(aux_buf->bo);
+ brw_bo_unreference(aux_buf->clear_color_bo);
free(aux_buf);
}
brw_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->r8stencil_mt);
- intel_miptree_aux_buffer_free((*mt)->hiz_buf);
- intel_miptree_aux_buffer_free((*mt)->mcs_buf);
+ intel_miptree_aux_buffer_free((*mt)->aux_buf);
free_aux_state_map((*mt)->aux_state);
intel_miptree_release(&(*mt)->plane[0]);
if (mt->etc_format != MESA_FORMAT_NONE)
mt_format = mt->etc_format;
- if (image->TexFormat != mt_format)
+ if (_mesa_get_srgb_format_linear(image->TexFormat) !=
+ _mesa_get_srgb_format_linear(mt_format))
return false;
intel_get_image_dims(image, &width, &height, &depth);
unsigned dst_level, unsigned dst_layer)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
mesa_format format = src_mt->format;
unsigned width = minify(src_mt->surf.phys_level0_sa.width,
src_level - src_mt->first_level);
assert(src_layer < get_num_phys_layers(&src_mt->surf,
src_level - src_mt->first_level));
- assert(src_mt->format == dst_mt->format);
+ assert(_mesa_get_srgb_format_linear(src_mt->format) ==
+ _mesa_get_srgb_format_linear(dst_mt->format));
+
+ DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
+ _mesa_get_format_name(src_mt->format),
+ src_mt, src_level, src_layer,
+ _mesa_get_format_name(dst_mt->format),
+ dst_mt, dst_level, dst_layer,
+ width, height);
+
+ if (devinfo->gen >= 6) {
+ /* On gen6 and above, we just use blorp. It's faster than the blitter
+ * and can handle everything without software fallbacks.
+ */
+ brw_blorp_copy_miptrees(brw,
+ src_mt, src_level, src_layer,
+ dst_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+
+ if (src_mt->stencil_mt) {
+ assert(dst_mt->stencil_mt);
+ brw_blorp_copy_miptrees(brw,
+ src_mt->stencil_mt, src_level, src_layer,
+ dst_mt->stencil_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+ }
+ return;
+ }
if (dst_mt->compressed) {
unsigned int i, j;
width = ALIGN_NPOT(width, i) / i;
}
- /* If it's a packed depth/stencil buffer with separate stencil, the blit
- * below won't apply since we can't do the depth's Y tiling or the
- * stencil's W tiling in the blitter.
- */
- if (src_mt->stencil_mt) {
- intel_miptree_copy_slice_sw(brw,
- src_mt, src_level, src_layer,
- dst_mt, dst_level, dst_layer,
- width, height);
- return;
- }
+ /* Gen4-5 doesn't support separate stencil */
+ assert(!src_mt->stencil_mt);
uint32_t dst_x, dst_y, src_x, src_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_layer,
if (!intel_miptree_blit(brw,
src_mt, src_level, src_layer, 0, 0, false,
dst_mt, dst_level, dst_layer, 0, 0, false,
- width, height, GL_COPY)) {
+ width, height, COLOR_LOGICOP_COPY)) {
perf_debug("miptree validate blit for %s failed\n",
_mesa_get_format_name(format));
/**
* Copies the image's current data to the given miptree, and associates that
* miptree with the image.
- *
- * If \c invalidate is true, then the actual image data does not need to be
- * copied, but the image still needs to be associated to the new miptree (this
- * is set to true if we're about to clear the image).
*/
void
intel_miptree_copy_teximage(struct brw_context *brw,
struct intel_texture_image *intelImage,
- struct intel_mipmap_tree *dst_mt,
- bool invalidate)
+ struct intel_mipmap_tree *dst_mt)
{
struct intel_mipmap_tree *src_mt = intelImage->mt;
struct intel_texture_object *intel_obj =
end_layer = intelImage->base.Base.Depth - 1;
}
- if (!invalidate) {
- for (unsigned i = start_layer; i <= end_layer; i++) {
- intel_miptree_copy_slice(brw,
- src_mt, level, i,
- dst_mt, level, i);
- }
+ for (unsigned i = start_layer; i <= end_layer; i++) {
+ intel_miptree_copy_slice(brw,
+ src_mt, level, i,
+ dst_mt, level, i);
}
intel_miptree_reference(&intelImage->mt, dst_mt);
intel_obj->needs_validate = true;
}
-static void
-intel_miptree_init_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- int init_value)
-{
- assert(mt->mcs_buf != NULL);
-
- /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
- *
- * When MCS buffer is enabled and bound to MSRT, it is required that it
- * is cleared prior to any rendering.
- *
- * Since we don't use the MCS buffer for any purpose other than rendering,
- * it makes sense to just clear it immediately upon allocation.
- *
- * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
- */
- void *map = brw_bo_map(brw, mt->mcs_buf->bo, MAP_WRITE);
- if (unlikely(map == NULL)) {
- fprintf(stderr, "Failed to map mcs buffer into GTT\n");
- brw_bo_unreference(mt->mcs_buf->bo);
- free(mt->mcs_buf);
- return;
- }
- void *data = map;
- memset(data, init_value, mt->mcs_buf->size);
- brw_bo_unmap(mt->mcs_buf->bo);
-}
-
static struct intel_miptree_aux_buffer *
intel_alloc_aux_buffer(struct brw_context *brw,
- const char *name,
const struct isl_surf *aux_surf,
- uint32_t alloc_flags,
- struct intel_mipmap_tree *mt)
+ bool wants_memset,
+ uint8_t memset_value)
{
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
if (!buf)
return false;
- buf->size = aux_surf->size;
- buf->pitch = aux_surf->row_pitch;
- buf->qpitch = isl_surf_get_array_pitch_sa_rows(aux_surf);
+ uint64_t size = aux_surf->size;
+
+ const bool has_indirect_clear = brw->isl_dev.ss.clear_color_state_size > 0;
+ if (has_indirect_clear) {
+ /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
+ * will set a pointer to a dword somewhere that contains the color. So,
+ * allocate the space for the clear color value here on the aux buffer.
+ */
+ buf->clear_color_offset = size;
+ size += brw->isl_dev.ss.clear_color_state_size;
+ }
+
+ /* If the buffer needs to be initialised (requiring the buffer to be
+ * immediately mapped to cpu space for writing), do not use the gpu access
+ * flag which can cause an unnecessary delay if the backing pages happened
+ * to be just used by the GPU.
+ */
+ const bool alloc_zeroed = wants_memset && memset_value == 0;
+ const bool needs_memset =
+ !alloc_zeroed && (wants_memset || has_indirect_clear);
+ const uint32_t alloc_flags =
+ alloc_zeroed ? BO_ALLOC_ZEROED : (needs_memset ? 0 : BO_ALLOC_BUSY);
/* ISL has stricter set of alignment rules then the drm allocator.
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
*/
- buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, buf->size,
- I915_TILING_Y, buf->pitch, alloc_flags);
+ buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "aux-miptree", size,
+ BRW_MEMZONE_OTHER, I915_TILING_Y,
+ aux_surf->row_pitch, alloc_flags);
if (!buf->bo) {
free(buf);
return NULL;
}
- buf->surf = *aux_surf;
-
- return buf;
-}
-
-static bool
-intel_miptree_alloc_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- GLuint num_samples)
-{
- assert(brw->gen >= 7); /* MCS only used on Gen7+ */
- assert(mt->mcs_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
+ /* Initialize the bo to the desired value */
+ if (needs_memset) {
+ assert(!(alloc_flags & BO_ALLOC_BUSY));
- /* Multisampled miptrees are only supported for single level. */
- assert(mt->first_level == 0);
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_CLEAR);
- if (!aux_state)
- return false;
+ void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
+ if (map == NULL) {
+ intel_miptree_aux_buffer_free(buf);
+ return NULL;
+ }
- struct isl_surf temp_mcs_surf;
+ /* Memset the aux_surf portion of the BO. */
+ if (wants_memset)
+ memset(map, memset_value, aux_surf->size);
- MAYBE_UNUSED bool ok =
- isl_surf_get_mcs_surf(&brw->isl_dev, &mt->surf, &temp_mcs_surf);
- assert(ok);
+ /* Zero the indirect clear color to match ::fast_clear_color. */
+ if (has_indirect_clear) {
+ memset((char *)map + buf->clear_color_offset, 0,
+ brw->isl_dev.ss.clear_color_state_size);
+ }
- /* Buffer needs to be initialised requiring the buffer to be immediately
- * mapped to cpu space for writing. Therefore do not use the gpu access
- * flag which can cause an unnecessary delay if the backing pages happened
- * to be just used by the GPU.
- */
- const uint32_t alloc_flags = 0;
- mt->mcs_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
- &temp_mcs_surf, alloc_flags, mt);
- if (!mt->mcs_buf) {
- free(aux_state);
- return false;
+ brw_bo_unmap(buf->bo);
}
- mt->aux_state = aux_state;
+ if (has_indirect_clear) {
+ buf->clear_color_bo = buf->bo;
+ brw_bo_reference(buf->clear_color_bo);
+ }
- intel_miptree_init_mcs(brw, mt, 0xFF);
+ buf->surf = *aux_surf;
- return true;
+ return buf;
}
-bool
-intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- assert(mt->mcs_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
- mt->aux_usage == ISL_AUX_USAGE_CCS_D);
-
- struct isl_surf temp_ccs_surf;
-
- if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &temp_ccs_surf, 0))
- return false;
-
- assert(temp_ccs_surf.size &&
- (temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
-
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_PASS_THROUGH);
- if (!aux_state)
- return false;
-
- /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
- * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
- *
- * "If Software wants to enable Color Compression without Fast clear,
- * Software needs to initialize MCS with zeros."
- *
- * A CCS value of 0 indicates that the corresponding block is in the
- * pass-through state which is what we want.
- *
- * For CCS_D, on the other hand, we don't care as we're about to perform a
- * fast-clear operation. In that case, being hot in caches more useful.
- */
- const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
- BO_ALLOC_ZEROED : BO_ALLOC_FOR_RENDER;
- mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
- &temp_ccs_surf, alloc_flags, mt);
- if (!mt->mcs_buf) {
- free(aux_state);
- return false;
- }
-
- mt->aux_state = aux_state;
-
- return true;
-}
/**
- * Helper for intel_miptree_alloc_hiz() that sets
+ * Helper for intel_miptree_alloc_aux() that sets
* \c mt->level[level].has_hiz. Return true if and only if
* \c has_hiz was set.
*/
struct intel_mipmap_tree *mt,
uint32_t level)
{
- assert(mt->hiz_buf);
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ assert(mt->aux_buf);
assert(mt->surf.size > 0);
- if (brw->gen >= 8 || brw->is_haswell) {
+ if (devinfo->gen >= 8 || devinfo->is_haswell) {
uint32_t width = minify(mt->surf.phys_level0_sa.width, level);
uint32_t height = minify(mt->surf.phys_level0_sa.height, level);
return true;
}
-bool
-intel_miptree_alloc_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- assert(mt->hiz_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
-
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
- if (!aux_state)
- return false;
-
- struct isl_surf temp_hiz_surf;
-
- MAYBE_UNUSED bool ok =
- isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &temp_hiz_surf);
- assert(ok);
-
- const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;
- mt->hiz_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
- &temp_hiz_surf, alloc_flags, mt);
-
- if (!mt->hiz_buf) {
- free(aux_state);
- return false;
- }
-
- for (unsigned level = mt->first_level; level <= mt->last_level; ++level)
- intel_miptree_level_enable_hiz(brw, mt, level);
-
- mt->aux_state = aux_state;
-
- return true;
-}
-
/**
* Allocate the initial aux surface for a miptree based on mt->aux_usage
* create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
* compress clear color so we wait until an actual fast-clear to allocate it.
*/
-static bool
+bool
intel_miptree_alloc_aux(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
+ assert(mt->aux_buf == NULL);
+
+ /* Get the aux buf allocation parameters for this miptree. */
+ enum isl_aux_state initial_state;
+ uint8_t memset_value;
+ struct isl_surf aux_surf;
+ MAYBE_UNUSED bool aux_surf_ok;
+
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
- return true;
-
+ aux_surf.size = 0;
+ aux_surf_ok = true;
+ break;
case ISL_AUX_USAGE_HIZ:
- assert(!_mesa_is_format_color_format(mt->format));
- if (!intel_miptree_alloc_hiz(brw, mt))
- return false;
- return true;
-
+ initial_state = ISL_AUX_STATE_AUX_INVALID;
+ aux_surf_ok = isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &aux_surf);
+ break;
case ISL_AUX_USAGE_MCS:
- assert(_mesa_is_format_color_format(mt->format));
- assert(mt->surf.samples > 1);
- if (!intel_miptree_alloc_mcs(brw, mt, mt->surf.samples))
- return false;
- return true;
-
+ /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
+ *
+ * When MCS buffer is enabled and bound to MSRT, it is required that
+ * it is cleared prior to any rendering.
+ *
+ * Since we don't use the MCS buffer for any purpose other than
+ * rendering, it makes sense to just clear it immediately upon
+ * allocation.
+ *
+ * Note: the clear value for MCS buffers is all 1's, so we memset to
+ * 0xff.
+ */
+ initial_state = ISL_AUX_STATE_CLEAR;
+ memset_value = 0xFF;
+ aux_surf_ok = isl_surf_get_mcs_surf(&brw->isl_dev, &mt->surf, &aux_surf);
+ break;
case ISL_AUX_USAGE_CCS_D:
- /* Since CCS_D can only compress clear color so we wait until an actual
- * fast-clear to allocate it.
+ case ISL_AUX_USAGE_CCS_E:
+ /* When CCS_E is used, we need to ensure that the CCS starts off in a
+ * valid state. From the Sky Lake PRM, "MCS Buffer for Render
+ * Target(s)":
+ *
+ * "If Software wants to enable Color Compression without Fast
+ * clear, Software needs to initialize MCS with zeros."
+ *
+ * A CCS value of 0 indicates that the corresponding block is in the
+ * pass-through state which is what we want.
+ *
+ * For CCS_D, do the same thing. On gen9+, this avoids having any
+ * undefined bits in the aux buffer.
*/
- return true;
+ initial_state = ISL_AUX_STATE_PASS_THROUGH;
+ memset_value = 0;
+ aux_surf_ok =
+ isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &aux_surf, 0);
+ break;
+ }
- case ISL_AUX_USAGE_CCS_E:
- assert(_mesa_is_format_color_format(mt->format));
- assert(mt->surf.samples == 1);
- if (!intel_miptree_alloc_ccs(brw, mt))
- return false;
+ /* We should have a valid aux_surf. */
+ assert(aux_surf_ok);
+
+ /* No work is needed for a zero-sized auxiliary buffer. */
+ if (aux_surf.size == 0)
return true;
+
+ /* Create the aux_state for the auxiliary buffer. */
+ mt->aux_state = create_aux_state_map(mt, initial_state);
+ if (mt->aux_state == NULL)
+ return false;
+
+ /* Allocate the auxiliary buffer. */
+ const bool needs_memset = initial_state != ISL_AUX_STATE_AUX_INVALID;
+ mt->aux_buf = intel_alloc_aux_buffer(brw, &aux_surf, needs_memset,
+ memset_value);
+ if (mt->aux_buf == NULL) {
+ free_aux_state_map(mt->aux_state);
+ mt->aux_state = NULL;
+ return false;
+ }
+
+ /* Perform aux_usage-specific initialization. */
+ if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
+ for (unsigned level = mt->first_level; level <= mt->last_level; ++level)
+ intel_miptree_level_enable_hiz(brw, mt, level);
}
- unreachable("Invalid aux usage");
+ return true;
}
intel_miptree_sample_with_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
- * so keep things conservative for now and never enable it unless we're SKL+.
- */
- if (brw->gen < 9) {
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (!devinfo->has_sample_with_hiz) {
return false;
}
- if (!mt->hiz_buf) {
+ if (!mt->aux_buf) {
return false;
}
{
assert(_mesa_is_format_color_format(mt->format));
- if (!mt->mcs_buf)
+ if (!mt->aux_buf)
return false;
/* Clamp the level range to fit the miptree */
const struct intel_mipmap_tree *mt,
unsigned level, unsigned layer)
{
-
- if (!mt->mcs_buf)
+ if (!mt->aux_buf)
return;
/* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
- assert(brw->gen >= 8 ||
+ assert(brw->screen->devinfo.gen >= 8 ||
(level == 0 && mt->first_level == 0 && mt->last_level == 0));
/* Compression of arrayed msaa surfaces is supported. */
return;
/* Fast color clear is supported for non-msaa arrays only on Gen8+. */
- assert(brw->gen >= 8 ||
+ assert(brw->screen->devinfo.gen >= 8 ||
(layer == 0 &&
mt->surf.logical_level0_px.depth == 1 &&
mt->surf.logical_level0_px.array_len == 1));
(void)layer;
}
-static enum blorp_fast_clear_op
+static enum isl_aux_op
get_ccs_d_resolve_op(enum isl_aux_state aux_state,
enum isl_aux_usage aux_usage,
bool fast_clear_supported)
case ISL_AUX_STATE_CLEAR:
case ISL_AUX_STATE_PARTIAL_CLEAR:
if (!ccs_supported)
- return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ return ISL_AUX_OP_FULL_RESOLVE;
else
- return BLORP_FAST_CLEAR_OP_NONE;
+ return ISL_AUX_OP_NONE;
case ISL_AUX_STATE_PASS_THROUGH:
- return BLORP_FAST_CLEAR_OP_NONE;
+ return ISL_AUX_OP_NONE;
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_AUX_INVALID:
unreachable("Invalid aux state for CCS_D");
}
-static enum blorp_fast_clear_op
+static enum isl_aux_op
get_ccs_e_resolve_op(enum isl_aux_state aux_state,
enum isl_aux_usage aux_usage,
bool fast_clear_supported)
case ISL_AUX_STATE_CLEAR:
case ISL_AUX_STATE_PARTIAL_CLEAR:
if (fast_clear_supported)
- return BLORP_FAST_CLEAR_OP_NONE;
+ return ISL_AUX_OP_NONE;
else if (aux_usage == ISL_AUX_USAGE_CCS_E)
- return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+ return ISL_AUX_OP_PARTIAL_RESOLVE;
else
- return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ return ISL_AUX_OP_FULL_RESOLVE;
case ISL_AUX_STATE_COMPRESSED_CLEAR:
if (aux_usage != ISL_AUX_USAGE_CCS_E)
- return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ return ISL_AUX_OP_FULL_RESOLVE;
else if (!fast_clear_supported)
- return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+ return ISL_AUX_OP_PARTIAL_RESOLVE;
else
- return BLORP_FAST_CLEAR_OP_NONE;
+ return ISL_AUX_OP_NONE;
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
if (aux_usage != ISL_AUX_USAGE_CCS_E)
- return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ return ISL_AUX_OP_FULL_RESOLVE;
else
- return BLORP_FAST_CLEAR_OP_NONE;
+ return ISL_AUX_OP_NONE;
case ISL_AUX_STATE_PASS_THROUGH:
- return BLORP_FAST_CLEAR_OP_NONE;
+ return ISL_AUX_OP_NONE;
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_AUX_INVALID:
{
enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, layer);
- enum blorp_fast_clear_op resolve_op;
+ enum isl_aux_op resolve_op;
if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
resolve_op = get_ccs_e_resolve_op(aux_state, aux_usage,
fast_clear_supported);
fast_clear_supported);
}
- if (resolve_op != BLORP_FAST_CLEAR_OP_NONE) {
+ if (resolve_op != ISL_AUX_OP_NONE) {
intel_miptree_check_color_resolve(brw, mt, level, layer);
brw_blorp_resolve_color(brw, mt, level, layer, resolve_op);
switch (resolve_op) {
- case BLORP_FAST_CLEAR_OP_RESOLVE_FULL:
+ case ISL_AUX_OP_FULL_RESOLVE:
/* The CCS full resolve operation destroys the CCS and sets it to the
* pass-through state. (You can also think of this as being both a
* resolve and an ambiguate in one operation.)
ISL_AUX_STATE_PASS_THROUGH);
break;
- case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL:
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
break;
{
assert(aux_usage == ISL_AUX_USAGE_NONE || aux_usage == ISL_AUX_USAGE_HIZ);
- enum blorp_hiz_op hiz_op = BLORP_HIZ_OP_NONE;
+ enum isl_aux_op hiz_op = ISL_AUX_OP_NONE;
switch (intel_miptree_get_aux_state(mt, level, layer)) {
case ISL_AUX_STATE_CLEAR:
case ISL_AUX_STATE_COMPRESSED_CLEAR:
if (aux_usage != ISL_AUX_USAGE_HIZ || !fast_clear_supported)
- hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
+ hiz_op = ISL_AUX_OP_FULL_RESOLVE;
break;
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
if (aux_usage != ISL_AUX_USAGE_HIZ)
- hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
+ hiz_op = ISL_AUX_OP_FULL_RESOLVE;
break;
case ISL_AUX_STATE_PASS_THROUGH:
case ISL_AUX_STATE_AUX_INVALID:
if (aux_usage == ISL_AUX_USAGE_HIZ)
- hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
+ hiz_op = ISL_AUX_OP_AMBIGUATE;
break;
case ISL_AUX_STATE_PARTIAL_CLEAR:
unreachable("Invalid HiZ state");
}
- if (hiz_op != BLORP_HIZ_OP_NONE) {
+ if (hiz_op != ISL_AUX_OP_NONE) {
intel_hiz_exec(brw, mt, level, layer, 1, hiz_op);
switch (hiz_op) {
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_RESOLVED);
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
/* The HiZ resolve operation is actually an ambiguate */
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_PASS_THROUGH);
break;
case ISL_AUX_USAGE_MCS:
- assert(mt->mcs_buf);
+ assert(mt->aux_buf);
assert(start_level == 0 && num_levels == 1);
const uint32_t level_layers =
miptree_layer_range_length(mt, 0, start_layer, num_layers);
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
- if (!mt->mcs_buf)
+ if (!mt->aux_buf)
return;
for (uint32_t l = 0; l < num_levels; l++) {
break;
case ISL_AUX_USAGE_HIZ:
- assert(mt->hiz_buf);
+ assert(mt->aux_buf);
for (uint32_t l = 0; l < num_levels; l++) {
const uint32_t level = start_level + l;
if (!intel_miptree_level_has_hiz(mt, level))
break;
case ISL_AUX_USAGE_MCS:
- assert(mt->mcs_buf);
+ assert(mt->aux_buf);
for (uint32_t a = 0; a < num_layers; a++) {
intel_miptree_finish_mcs_write(brw, mt, start_layer + a,
aux_usage);
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
- if (!mt->mcs_buf)
+ if (!mt->aux_buf)
return;
for (uint32_t a = 0; a < num_layers; a++) {
intel_miptree_check_level_layer(mt, level, layer);
if (_mesa_is_format_color_format(mt->format)) {
- assert(mt->mcs_buf != NULL);
+ assert(mt->aux_buf != NULL);
assert(mt->surf.samples == 1 ||
mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
if (_mesa_is_format_color_format(mt->format)) {
- assert(mt->mcs_buf != NULL);
+ assert(mt->aux_buf != NULL);
assert(mt->surf.samples == 1 ||
mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
assert(intel_miptree_level_has_hiz(mt, level));
}
- for (unsigned a = 0; a < num_layers; a++)
- mt->aux_state[level][start_layer + a] = aux_state;
+ for (unsigned a = 0; a < num_layers; a++) {
+ if (mt->aux_state[level][start_layer + a] != aux_state) {
+ mt->aux_state[level][start_layer + a] = aux_state;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
+ }
+ }
}
/* On Gen9 color buffers may be compressed by the hardware (lossless
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return false;
- if (!isl_formats_are_ccs_e_compatible(&brw->screen->devinfo,
- mt->surf.format, view_format)) {
+ if (!format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
+ mt, view_format)) {
perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
isl_format_get_layout(view_format)->name,
_mesa_get_format_name(mt->format));
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
- if (mt->mcs_buf && can_texture_with_ccs(brw, mt, view_format))
+ if (!mt->aux_buf) {
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
+ return ISL_AUX_USAGE_NONE;
+ }
+
+ /* If we don't have any unresolved color, report an aux usage of
+ * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
+ * aux surface and we can save some bandwidth.
+ */
+ if (!intel_miptree_has_color_unresolved(mt, 0, INTEL_REMAINING_LEVELS,
+ 0, INTEL_REMAINING_LAYERS))
+ return ISL_AUX_USAGE_NONE;
+
+ if (can_texture_with_ccs(brw, mt, view_format))
return ISL_AUX_USAGE_CCS_E;
break;
return isl_format_srgb_to_linear(a) == isl_format_srgb_to_linear(b);
}
-static void
-intel_miptree_prepare_texture_slices(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- enum isl_format view_format,
- uint32_t start_level, uint32_t num_levels,
- uint32_t start_layer, uint32_t num_layers,
- bool *aux_supported_out)
+void
+intel_miptree_prepare_texture(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ enum isl_format view_format,
+ uint32_t start_level, uint32_t num_levels,
+ uint32_t start_layer, uint32_t num_layers)
{
enum isl_aux_usage aux_usage =
intel_miptree_texture_aux_usage(brw, mt, view_format);
intel_miptree_prepare_access(brw, mt, start_level, num_levels,
start_layer, num_layers,
aux_usage, clear_supported);
- if (aux_supported_out)
- *aux_supported_out = aux_usage != ISL_AUX_USAGE_NONE;
-}
-
-void
-intel_miptree_prepare_texture(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- enum isl_format view_format,
- bool *aux_supported_out)
-{
- intel_miptree_prepare_texture_slices(brw, mt, view_format,
- 0, INTEL_REMAINING_LEVELS,
- 0, INTEL_REMAINING_LAYERS,
- aux_supported_out);
}
void
ISL_AUX_USAGE_NONE, false);
}
-void
-intel_miptree_prepare_fb_fetch(struct brw_context *brw,
- struct intel_mipmap_tree *mt, uint32_t level,
- uint32_t start_layer, uint32_t num_layers)
-{
- intel_miptree_prepare_texture_slices(brw, mt, mt->surf.format, level, 1,
- start_layer, num_layers, NULL);
-}
-
enum isl_aux_usage
intel_miptree_render_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- bool srgb_enabled, bool blend_enabled)
+ enum isl_format render_format,
+ bool blend_enabled,
+ bool draw_aux_disabled)
{
+ struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (draw_aux_disabled)
+ return ISL_AUX_USAGE_NONE;
+
switch (mt->aux_usage) {
case ISL_AUX_USAGE_MCS:
- assert(mt->mcs_buf);
+ assert(mt->aux_buf);
return ISL_AUX_USAGE_MCS;
case ISL_AUX_USAGE_CCS_D:
- return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
-
- case ISL_AUX_USAGE_CCS_E: {
- mesa_format mesa_format =
- srgb_enabled ? mt->format :_mesa_get_srgb_format_linear(mt->format);
- enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+ case ISL_AUX_USAGE_CCS_E:
+ if (!mt->aux_buf) {
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
+ return ISL_AUX_USAGE_NONE;
+ }
- /* If the format supports CCS_E, then we can just use it */
- if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format))
- return ISL_AUX_USAGE_CCS_E;
-
- /* Otherwise, we have to fall back to CCS_D */
-
- /* gen9 hardware technically supports non-0/1 clear colors with sRGB
+ /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
* formats. However, there are issues with blending where it doesn't
* properly apply the sRGB curve to the clear color when blending.
*/
- if (blend_enabled && isl_format_is_srgb(isl_format) &&
- !isl_color_value_is_zero_one(mt->fast_clear_color, isl_format))
+ if (devinfo->gen >= 9 && blend_enabled &&
+ isl_format_is_srgb(render_format) &&
+ !isl_color_value_is_zero_one(mt->fast_clear_color, render_format))
return ISL_AUX_USAGE_NONE;
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E &&
+ format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
+ mt, render_format))
+ return ISL_AUX_USAGE_CCS_E;
+
+ /* Otherwise, we have to fall back to CCS_D */
return ISL_AUX_USAGE_CCS_D;
- }
default:
return ISL_AUX_USAGE_NONE;
intel_miptree_prepare_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled, bool blend_enabled)
+ enum isl_aux_usage aux_usage)
{
- enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, mt, srgb_enabled, blend_enabled);
intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
aux_usage, aux_usage != ISL_AUX_USAGE_NONE);
}
intel_miptree_finish_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled, bool blend_enabled)
+ enum isl_aux_usage aux_usage)
{
assert(_mesa_is_format_color_format(mt->format));
- enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, mt, srgb_enabled, blend_enabled);
intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
aux_usage);
}
uint32_t start_layer, uint32_t layer_count)
{
intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
- mt->aux_usage, mt->hiz_buf != NULL);
+ mt->aux_usage, mt->aux_buf != NULL);
}
void
{
if (depth_written) {
intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
- mt->hiz_buf != NULL);
+ mt->aux_buf != NULL);
}
}
+void
+intel_miptree_prepare_external(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
+ bool supports_fast_clear = false;
+
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(mt->drm_modifier);
+
+ if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* CCS_E is the only supported aux for external images and it's only
+ * supported on very simple images.
+ */
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+ assert(_mesa_is_format_color_format(mt->format));
+ assert(mt->first_level == 0 && mt->last_level == 0);
+ assert(mt->surf.logical_level0_px.depth == 1);
+ assert(mt->surf.logical_level0_px.array_len == 1);
+ assert(mt->surf.samples == 1);
+ assert(mt->aux_buf != NULL);
+
+ aux_usage = mod_info->aux_usage;
+ supports_fast_clear = mod_info->supports_clear_color;
+ }
+
+ intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
+ 0, INTEL_REMAINING_LAYERS,
+ aux_usage, supports_fast_clear);
+}
+
+void
+intel_miptree_finish_external(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ if (!mt->aux_buf)
+ return;
+
+ /* We don't know the actual aux state of the aux surface. The previous
+ * owner could have given it to us in a number of different states.
+ * Because we don't know the aux state, we reset the aux state to the
+ * least common denominator of possible valid states.
+ */
+ enum isl_aux_state default_aux_state =
+ isl_drm_modifier_get_default_aux_state(mt->drm_modifier);
+ assert(mt->last_level == mt->first_level);
+ intel_miptree_set_aux_state(brw, mt, 0, 0, INTEL_REMAINING_LAYERS,
+ default_aux_state);
+}
+
/**
* Make it possible to share the BO backing the given miptree with another
* process or another miptree.
0, INTEL_REMAINING_LAYERS,
ISL_AUX_USAGE_NONE, false);
- if (mt->mcs_buf) {
- brw_bo_unreference(mt->mcs_buf->bo);
- free(mt->mcs_buf);
- mt->mcs_buf = NULL;
-
- /* Any pending MCS/CCS operations are no longer needed. Trying to
- * execute any will likely crash due to the missing aux buffer. So let's
- * delete all pending ops.
- */
- free(mt->aux_state);
- mt->aux_state = NULL;
- }
-
- if (mt->hiz_buf) {
- intel_miptree_aux_buffer_free(mt->hiz_buf);
- mt->hiz_buf = NULL;
+ if (mt->aux_buf) {
+ intel_miptree_aux_buffer_free(mt->aux_buf);
+ mt->aux_buf = NULL;
+ /* Make future calls of intel_miptree_level_has_hiz() return false. */
for (uint32_t l = mt->first_level; l <= mt->last_level; ++l) {
mt->level[l].has_hiz = false;
}
- /* Any pending HiZ operations are no longer needed. Trying to execute
- * any will likely crash due to the missing aux buffer. So let's delete
- * all pending ops.
- */
free(mt->aux_state);
mt->aux_state = NULL;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
}
mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
}
intel_update_r8stencil(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- assert(brw->gen >= 7);
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ assert(devinfo->gen >= 7);
struct intel_mipmap_tree *src =
mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt;
- if (!src || brw->gen >= 8 || !src->r8stencil_needs_update)
+ if (!src || devinfo->gen >= 8 || !src->r8stencil_needs_update)
return;
assert(src->surf.size > 0);
if (!mt->r8stencil_mt) {
- assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
+ assert(devinfo->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
mt->r8stencil_mt = make_surface(
brw,
src->target,
src->surf.samples,
ISL_TILING_Y0_BIT,
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, 0, NULL);
+ BO_ALLOC_BUSY, 0, NULL);
assert(mt->r8stencil_mt);
}
}
}
- brw_render_cache_set_check_flush(brw, dst->bo);
+ brw_cache_flush_for_read(brw, dst->bo);
src->r8stencil_needs_update = false;
}
brw_bo_unmap(mt->bo);
}
+static void
+intel_miptree_unmap_gtt(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level, unsigned int slice)
+{
+ intel_miptree_unmap_raw(mt);
+}
+
static void
intel_miptree_map_gtt(struct brw_context *brw,
struct intel_mipmap_tree *mt,
map->x, map->y, map->w, map->h,
mt, _mesa_get_format_name(mt->format),
x, y, map->ptr, map->stride);
+
+ map->unmap = intel_miptree_unmap_gtt;
}
static void
-intel_miptree_unmap_gtt(struct intel_mipmap_tree *mt)
+intel_miptree_unmap_blit(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
{
- intel_miptree_unmap_raw(mt);
+ struct gl_context *ctx = &brw->ctx;
+
+ intel_miptree_unmap_raw(map->linear_mt);
+
+ if (map->mode & GL_MAP_WRITE_BIT) {
+ bool ok = intel_miptree_copy(brw,
+ map->linear_mt, 0, 0, 0, 0,
+ mt, level, slice, map->x, map->y,
+ map->w, map->h);
+ WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+ }
+
+ intel_miptree_release(&map->linear_mt);
}
static void
/* last_level */ 0,
map->w, map->h, 1,
/* samples */ 1,
- MIPTREE_LAYOUT_TILING_NONE);
+ MIPTREE_CREATE_LINEAR);
if (!map->linear_mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
mt, _mesa_get_format_name(mt->format),
level, slice, map->ptr, map->stride);
+ map->unmap = intel_miptree_unmap_blit;
return;
fail:
map->stride = 0;
}
-static void
-intel_miptree_unmap_blit(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
-{
- struct gl_context *ctx = &brw->ctx;
-
- intel_miptree_unmap_raw(map->linear_mt);
-
- if (map->mode & GL_MAP_WRITE_BIT) {
- bool ok = intel_miptree_copy(brw,
- map->linear_mt, 0, 0, 0, 0,
- mt, level, slice, map->x, map->y,
- map->w, map->h);
- WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
- }
-
- intel_miptree_release(&map->linear_mt);
-}
-
/**
* "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
*/
#if defined(USE_SSE41)
+static void
+intel_miptree_unmap_movntdqa(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
+{
+ _mesa_align_free(map->buffer);
+ map->buffer = NULL;
+ map->ptr = NULL;
+}
+
static void
intel_miptree_map_movntdqa(struct brw_context *brw,
struct intel_mipmap_tree *mt,
}
intel_miptree_unmap_raw(mt);
+
+ map->unmap = intel_miptree_unmap_movntdqa;
}
+#endif
static void
-intel_miptree_unmap_movntdqa(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
+intel_miptree_unmap_s8(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
{
- _mesa_align_free(map->buffer);
- map->buffer = NULL;
- map->ptr = NULL;
+ if (map->mode & GL_MAP_WRITE_BIT) {
+ unsigned int image_x, image_y;
+ uint8_t *untiled_s8_map = map->ptr;
+ uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT);
+
+ intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
+
+ for (uint32_t y = 0; y < map->h; y++) {
+ for (uint32_t x = 0; x < map->w; x++) {
+ ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch,
+ image_x + x + map->x,
+ image_y + y + map->y,
+ brw->has_swizzling);
+ tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
+ }
+ }
+
+ intel_miptree_unmap_raw(mt);
+ }
+
+ free(map->buffer);
}
-#endif
static void
intel_miptree_map_s8(struct brw_context *brw,
map->x, map->y, map->w, map->h,
mt, map->ptr, map->stride);
}
-}
-
-static void
-intel_miptree_unmap_s8(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
-{
- if (map->mode & GL_MAP_WRITE_BIT) {
- unsigned int image_x, image_y;
- uint8_t *untiled_s8_map = map->ptr;
- uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT);
-
- intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
-
- for (uint32_t y = 0; y < map->h; y++) {
- for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch,
- image_x + x + map->x,
- image_y + y + map->y,
- brw->has_swizzling);
- tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
- }
- }
-
- intel_miptree_unmap_raw(mt);
- }
-
- free(map->buffer);
-}
-
-static void
-intel_miptree_map_etc(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
-{
- assert(mt->etc_format != MESA_FORMAT_NONE);
- if (mt->etc_format == MESA_FORMAT_ETC1_RGB8) {
- assert(mt->format == MESA_FORMAT_R8G8B8X8_UNORM);
- }
-
- assert(map->mode & GL_MAP_WRITE_BIT);
- assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
- map->stride = _mesa_format_row_stride(mt->etc_format, map->w);
- map->buffer = malloc(_mesa_format_image_size(mt->etc_format,
- map->w, map->h, 1));
- map->ptr = map->buffer;
+ map->unmap = intel_miptree_unmap_s8;
}
static void
free(map->buffer);
}
+static void
+intel_miptree_map_etc(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
+{
+ assert(mt->etc_format != MESA_FORMAT_NONE);
+ if (mt->etc_format == MESA_FORMAT_ETC1_RGB8) {
+ assert(mt->format == MESA_FORMAT_R8G8B8X8_UNORM);
+ }
+
+ assert(map->mode & GL_MAP_WRITE_BIT);
+ assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
+
+ map->stride = _mesa_format_row_stride(mt->etc_format, map->w);
+ map->buffer = malloc(_mesa_format_image_size(mt->etc_format,
+ map->w, map->h, 1));
+ map->ptr = map->buffer;
+ map->unmap = intel_miptree_unmap_etc;
+}
+
/**
- * Mapping function for packed depth/stencil miptrees backed by real separate
+ * Mapping functions for packed depth/stencil miptrees backed by real separate
* miptrees for depth and stencil.
*
* On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
* copying the data between the actual backing store and the temporary.
*/
static void
-intel_miptree_map_depthstencil(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level, unsigned int slice)
+intel_miptree_unmap_depthstencil(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
{
struct intel_mipmap_tree *z_mt = mt;
struct intel_mipmap_tree *s_mt = mt->stencil_mt;
bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
- int packed_bpp = map_z32f_x24s8 ? 8 : 4;
- map->stride = map->w * packed_bpp;
- map->buffer = map->ptr = malloc(map->stride * map->h);
- if (!map->buffer)
- return;
-
- /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
- * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
- * invalidate is set, since we'll be writing the whole rectangle from our
- * temporary buffer back out.
- */
- if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
+ if (map->mode & GL_MAP_WRITE_BIT) {
uint32_t *packed_map = map->ptr;
- uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_READ_BIT);
- uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_READ_BIT);
+ uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_WRITE_BIT);
+ uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_WRITE_BIT);
unsigned int s_image_x, s_image_y;
unsigned int z_image_x, z_image_y;
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- int map_x = map->x + x, map_y = map->y + y;
ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch,
- map_x + s_image_x,
- map_y + s_image_y,
+ x + s_image_x + map->x,
+ y + s_image_y + map->y,
brw->has_swizzling);
- ptrdiff_t z_offset = ((map_y + z_image_y) *
+ ptrdiff_t z_offset = ((y + z_image_y + map->y) *
(z_mt->surf.row_pitch / 4) +
- (map_x + z_image_x));
- uint8_t s = s_map[s_offset];
- uint32_t z = z_map[z_offset];
+ (x + z_image_x + map->x));
if (map_z32f_x24s8) {
- packed_map[(y * map->w + x) * 2 + 0] = z;
- packed_map[(y * map->w + x) * 2 + 1] = s;
+ z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
+ s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1];
} else {
- packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff);
+ uint32_t packed = packed_map[y * map->w + x];
+ s_map[s_offset] = packed >> 24;
+ z_map[z_offset] = packed;
}
}
}
intel_miptree_unmap_raw(s_mt);
intel_miptree_unmap_raw(z_mt);
- DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
+ DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
__func__,
map->x, map->y, map->w, map->h,
- z_mt, map->x + z_image_x, map->y + z_image_y,
+ z_mt, _mesa_get_format_name(z_mt->format),
+ map->x + z_image_x, map->y + z_image_y,
s_mt, map->x + s_image_x, map->y + s_image_y,
map->ptr, map->stride);
- } else {
- DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__,
- map->x, map->y, map->w, map->h,
- mt, map->ptr, map->stride);
}
+
+ free(map->buffer);
}
static void
-intel_miptree_unmap_depthstencil(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
+intel_miptree_map_depthstencil(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level, unsigned int slice)
{
struct intel_mipmap_tree *z_mt = mt;
struct intel_mipmap_tree *s_mt = mt->stencil_mt;
bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
+ int packed_bpp = map_z32f_x24s8 ? 8 : 4;
- if (map->mode & GL_MAP_WRITE_BIT) {
+ map->stride = map->w * packed_bpp;
+ map->buffer = map->ptr = malloc(map->stride * map->h);
+ if (!map->buffer)
+ return;
+
+ /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
+ * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
+ * invalidate is set, since we'll be writing the whole rectangle from our
+ * temporary buffer back out.
+ */
+ if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
uint32_t *packed_map = map->ptr;
- uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_WRITE_BIT);
- uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_WRITE_BIT);
+ uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_READ_BIT);
+ uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_READ_BIT);
unsigned int s_image_x, s_image_y;
unsigned int z_image_x, z_image_y;
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
+ int map_x = map->x + x, map_y = map->y + y;
ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch,
- x + s_image_x + map->x,
- y + s_image_y + map->y,
+ map_x + s_image_x,
+ map_y + s_image_y,
brw->has_swizzling);
- ptrdiff_t z_offset = ((y + z_image_y + map->y) *
+ ptrdiff_t z_offset = ((map_y + z_image_y) *
(z_mt->surf.row_pitch / 4) +
- (x + z_image_x + map->x));
+ (map_x + z_image_x));
+ uint8_t s = s_map[s_offset];
+ uint32_t z = z_map[z_offset];
if (map_z32f_x24s8) {
- z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
- s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1];
+ packed_map[(y * map->w + x) * 2 + 0] = z;
+ packed_map[(y * map->w + x) * 2 + 1] = s;
} else {
- uint32_t packed = packed_map[y * map->w + x];
- s_map[s_offset] = packed >> 24;
- z_map[z_offset] = packed;
+ packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff);
}
}
}
intel_miptree_unmap_raw(s_mt);
intel_miptree_unmap_raw(z_mt);
- DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
+ DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
__func__,
map->x, map->y, map->w, map->h,
- z_mt, _mesa_get_format_name(z_mt->format),
- map->x + z_image_x, map->y + z_image_y,
+ z_mt, map->x + z_image_x, map->y + z_image_y,
s_mt, map->x + s_image_x, map->y + s_image_y,
map->ptr, map->stride);
+ } else {
+ DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__,
+ map->x, map->y, map->w, map->h,
+ mt, map->ptr, map->stride);
}
- free(map->buffer);
+ map->unmap = intel_miptree_unmap_depthstencil;
}
/**
unsigned int level,
unsigned int slice)
{
- if (brw->has_llc &&
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (devinfo->has_llc &&
/* It's probably not worth swapping to the blit ring because of
* all the overhead involved.
*/
!mt->compressed &&
(mt->surf.tiling == ISL_TILING_X ||
/* Prior to Sandybridge, the blitter can't handle Y tiling */
- (brw->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) ||
+ (devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) ||
/* Fast copy blit on skl+ supports all tiling formats. */
- brw->gen >= 9) &&
+ devinfo->gen >= 9) &&
can_blit_slice(mt, level, slice))
return true;
DBG("%s: mt %p (%s) level %d slice %d\n", __func__,
mt, _mesa_get_format_name(mt->format), level, slice);
- if (mt->format == MESA_FORMAT_S_UINT8) {
- intel_miptree_unmap_s8(brw, mt, map, level, slice);
- } else if (mt->etc_format != MESA_FORMAT_NONE &&
- !(map->mode & BRW_MAP_DIRECT_BIT)) {
- intel_miptree_unmap_etc(brw, mt, map, level, slice);
- } else if (mt->stencil_mt && !(map->mode & BRW_MAP_DIRECT_BIT)) {
- intel_miptree_unmap_depthstencil(brw, mt, map, level, slice);
- } else if (map->linear_mt) {
- intel_miptree_unmap_blit(brw, mt, map, level, slice);
-#if defined(USE_SSE41)
- } else if (map->buffer && cpu_has_sse4_1) {
- intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);
-#endif
- } else {
- intel_miptree_unmap_gtt(mt);
- }
+ if (map->unmap)
+ map->unmap(brw, mt, map, level, slice);
intel_miptree_release_map(mt, level, slice);
}
unreachable("Invalid texture target");
}
-enum isl_aux_usage
-intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
-{
- if (mt->hiz_buf)
- return ISL_AUX_USAGE_HIZ;
+bool
+intel_miptree_set_clear_color(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ union isl_color_value clear_color)
+{
+ if (memcmp(&mt->fast_clear_color, &clear_color, sizeof(clear_color)) != 0) {
+ mt->fast_clear_color = clear_color;
+ if (mt->aux_buf->clear_color_bo) {
+ /* We can't update the clear color while the hardware is still using
+ * the previous one for a resolve or sampling from it. Make sure that
+ * there are no pending commands at this point.
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+ for (int i = 0; i < 4; i++) {
+ brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
+ mt->aux_buf->clear_color_offset + i * 4,
+ mt->fast_clear_color.u32[i]);
+ }
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+ }
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
+ return true;
+ }
+ return false;
+}
- if (!mt->mcs_buf)
- return ISL_AUX_USAGE_NONE;
+union isl_color_value
+intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
+ const struct intel_mipmap_tree *mt,
+ enum isl_format view_format, bool sampling,
+ struct brw_bo **clear_color_bo,
+ uint32_t *clear_color_offset)
+{
+ assert(mt->aux_buf);
- return mt->aux_usage;
+ if (devinfo->gen == 10 && isl_format_is_srgb(view_format) && sampling) {
+ /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
+ * we switch to using the inline clear color and do the sRGB color
+ * conversion process defined in the OpenGL spec. The red, green, and
+ * blue channels take part in gamma correction, while the alpha channel
+ * is unchanged.
+ */
+ union isl_color_value srgb_decoded_value = mt->fast_clear_color;
+ for (unsigned i = 0; i < 3; i++) {
+ srgb_decoded_value.f32[i] =
+ util_format_srgb_to_linear_float(mt->fast_clear_color.f32[i]);
+ }
+ *clear_color_bo = 0;
+ *clear_color_offset = 0;
+ return srgb_decoded_value;
+ } else {
+ *clear_color_bo = mt->aux_buf->clear_color_bo;
+ *clear_color_offset = mt->aux_buf->clear_color_offset;
+ return mt->fast_clear_color;
+ }
}
projects / mesa.git / blobdiff