static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, gl_format format, GLenum target)
{
- struct intel_context *intel = &brw->intel;
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
- if (intel->gen < 7)
+ if (brw->gen < 7)
return INTEL_MSAA_LAYOUT_IMS;
/* In Gen7, IMS layout is only used for depth and stencil buffers. */
*/
if (_mesa_get_format_datatype(format) == GL_INT) {
/* TODO: is this workaround needed for future chipsets? */
- assert(intel->gen == 7);
+ assert(brw->gen == 7);
return INTEL_MSAA_LAYOUT_UMS;
} else {
/* For now, if we're going to be texturing from this surface,
intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- struct intel_context *intel = &brw->intel;
-
/* MCS support does not exist prior to Gen7 */
- if (intel->gen < 7)
+ if (brw->gen < 7)
return false;
/* MCS is only supported for color buffers */
bool for_bo,
GLuint num_samples)
{
- struct intel_context *intel = &brw->intel;
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
if (!for_bo &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
- (intel->must_use_separate_stencil ||
- (intel->has_separate_stencil &&
- brw_is_hiz_depth_format(brw, format)))) {
+ (brw->must_use_separate_stencil ||
+ (brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
mt->stencil_mt = intel_miptree_create(brw,
mt->target,
MESA_FORMAT_S8,
enum intel_miptree_tiling_mode requested,
struct intel_mipmap_tree *mt)
{
- struct intel_context *intel = &brw->intel;
if (format == MESA_FORMAT_S8) {
/* The stencil buffer is W tiled. However, we request from the kernel a
* non-tiled buffer because the GTT is incapable of W fencing.
}
/* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
- if (intel->gen < 6)
+ if (brw->gen < 6)
+ return I915_TILING_X;
+
+ /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
+ * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
+ * or Linear."
+ * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
+ * all the way back to 965, but is explicitly permitted on Gen7.
+ */
+ if (brw->gen != 7 && mt->cpp >= 16)
return I915_TILING_X;
return I915_TILING_Y | I915_TILING_X;
GLuint num_samples,
enum intel_miptree_tiling_mode requested_tiling)
{
- struct intel_context *intel = &brw->intel;
struct intel_mipmap_tree *mt;
gl_format tex_format = format;
gl_format etc_format = MESA_FORMAT_NONE;
GLuint total_width, total_height;
- if (!intel->is_baytrail) {
+ if (!brw->is_baytrail) {
switch (format) {
case MESA_FORMAT_ETC1_RGB8:
format = MESA_FORMAT_RGBX8888_REV;
uint32_t num_samples,
struct intel_region *region)
{
- struct intel_context *intel = &brw->intel;
struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
struct intel_mipmap_tree *mt,
GLuint num_samples)
{
- struct intel_context *intel = &brw->intel;
- assert(intel->gen >= 7); /* MCS only used on Gen7+ */
+ assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_mt == NULL);
/* Choose the correct format for the MCS buffer. All that really matters
uint32_t level,
uint32_t layer)
{
- struct intel_context *intel = &brw->intel;
assert(mt->hiz_mt);
- if (intel->is_haswell) {
- /* Disable HiZ for some slices to work around a hardware bug.
- *
- * Haswell hardware fails to respect
- * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y when during HiZ
- * ambiguate operations. The failure is inconsistent and affected by
- * other GPU contexts. Running a heavy GPU workload in a separate
- * process causes the failure rate to drop to nearly 0.
- *
- * To workaround the bug, we enable HiZ only when we can guarantee that
- * the Depth Coordinate Offset fields will be set to 0. The function
- * brw_get_depthstencil_tile_masks() is used to calculate the fields,
- * and the function is sometimes called in such a way that the presence
- * of an attached stencil buffer changes the fuction's return value.
- *
- * The largest tile size considered by brw_get_depthstencil_tile_masks()
- * is that of the stencil buffer. Therefore, if this hiz slice's
- * corresponding depth slice has an offset that is aligned to the
- * stencil buffer tile size, 64x64 pixels, then
- * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y is set to 0.
+ if (brw->is_haswell) {
+ const struct intel_mipmap_level *l = &mt->level[level];
+
+ /* Disable HiZ for LOD > 0 unless the width is 8 aligned
+ * and the height is 4 aligned. This allows our HiZ support
+ * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
+ * we can grow the width & height to allow the HiZ op to
+ * force the proper size alignments.
*/
- uint32_t depth_x_offset = mt->level[level].slice[layer].x_offset;
- uint32_t depth_y_offset = mt->level[level].slice[layer].y_offset;
- if ((depth_x_offset & 63) || (depth_y_offset & 63)) {
+ if (level > 0 && ((l->width & 7) || (l->height & 3))) {
return false;
}
}
level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
}
+void
+intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
+ uint32_t level)
+{
+ uint32_t layer;
+ uint32_t end_layer = mt->level[level].depth;
+
+ for (layer = 0; layer < end_layer; layer++) {
+ intel_miptree_slice_set_needs_depth_resolve(mt, level, layer);
+ }
+}
+
static bool
intel_miptree_slice_resolve(struct brw_context *brw,
struct intel_mipmap_tree *mt,
width, height,
dst_x0, dst_y0,
width, height,
- false, false /*mirror x, y*/);
+ GL_NEAREST, false, false /*mirror x, y*/);
if (src->stencil_mt) {
brw_blorp_blit_miptrees(brw,
width, height,
dst_x0, dst_y0,
width, height,
- false, false /*mirror x, y*/);
+ GL_NEAREST, false, false /*mirror x, y*/);
}
}
void *
intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
/* CPU accesses to color buffers don't understand fast color clears, so
* resolve any pending fast color clears before we map.
*/
if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
if (drm_intel_bo_busy(bo)) {
- perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
+ perf_debug("Mapping a busy miptree, causing a stall on the GPU.\n");
}
}
- intel_flush(ctx);
+ intel_batchbuffer_flush(brw);
if (mt->region->tiling != I915_TILING_NONE)
drm_intel_gem_bo_map_gtt(bo);
goto fail;
}
- intel_batchbuffer_flush(brw);
map->ptr = intel_miptree_map_raw(brw, map->mt);
DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__,
unsigned int level,
unsigned int slice)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
intel_miptree_unmap_raw(brw, map->mt);
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
{
- struct intel_context *intel = &brw->intel;
map->stride = map->w;
map->buffer = map->ptr = malloc(map->stride * map->h);
if (!map->buffer)
ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
x + image_x + map->x,
y + image_y + map->y,
- intel->has_swizzling);
+ brw->has_swizzling);
untiled_s8_map[y * map->w + x] = tiled_s8_map[offset];
}
}
unsigned int level,
unsigned int slice)
{
- struct intel_context *intel = &brw->intel;
if (map->mode & GL_MAP_WRITE_BIT) {
unsigned int image_x, image_y;
uint8_t *untiled_s8_map = map->ptr;
ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
x + map->x,
y + map->y,
- intel->has_swizzling);
+ brw->has_swizzling);
tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
}
}
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
{
- struct intel_context *intel = &brw->intel;
struct intel_mipmap_tree *z_mt = mt;
struct intel_mipmap_tree *s_mt = mt->stencil_mt;
bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT;
ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
map_x + s_image_x,
map_y + s_image_y,
- intel->has_swizzling);
+ brw->has_swizzling);
ptrdiff_t z_offset = ((map_y + z_image_y) *
(z_mt->region->pitch / 4) +
(map_x + z_image_x));
unsigned int level,
unsigned int slice)
{
- struct intel_context *intel = &brw->intel;
struct intel_mipmap_tree *z_mt = mt;
struct intel_mipmap_tree *s_mt = mt->stencil_mt;
bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT;
ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
x + s_image_x + map->x,
y + s_image_y + map->y,
- intel->has_swizzling);
+ brw->has_swizzling);
ptrdiff_t z_offset = ((y + z_image_y) *
(z_mt->region->pitch / 4) +
(x + z_image_x));
void **out_ptr,
int *out_stride)
{
- struct intel_context *intel = &brw->intel;
struct intel_miptree_map *map;
assert(mt->num_samples <= 1);
intel_miptree_map_depthstencil(brw, mt, map, level, slice);
}
/* See intel_miptree_blit() for details on the 32k pitch limit. */
- else if (intel->has_llc &&
+ else if (brw->has_llc &&
!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
(mt->region->tiling == I915_TILING_X ||
- (intel->gen >= 6 && mt->region->tiling == I915_TILING_Y)) &&
+ (brw->gen >= 6 && mt->region->tiling == I915_TILING_Y)) &&
mt->region->pitch < 32768) {
intel_miptree_map_blit(brw, mt, map, level, slice);
} else if (mt->region->tiling != I915_TILING_NONE &&
void **out_ptr,
int *out_stride)
{
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
struct intel_miptree_map *map;
assert(mt->num_samples > 1);
projects / mesa.git / blobdiff