i965: Move depth to the new resolve functions
[mesa.git] / src / mesa / drivers / dri / i965 / intel_mipmap_tree.c
index a60fac5250616a899f5dd0295df9e9ff6ef4ae1a..3d207328356149d9b237380b120f305bec912b36 100644 (file)
@@ -1386,7 +1386,7 @@ intel_miptree_init_mcs(struct brw_context *brw,
     *
     * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
     */
-   void *map = brw_bo_map_gtt(brw, mt->mcs_buf->bo, MAP_READ | MAP_WRITE);
+   void *map = brw_bo_map(brw, mt->mcs_buf->bo, MAP_WRITE);
    if (unlikely(map == NULL)) {
       fprintf(stderr, "Failed to map mcs buffer into GTT\n");
       brw_bo_unreference(mt->mcs_buf->bo);
@@ -1977,23 +1977,30 @@ intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 }
 
 static bool
-intel_miptree_slice_resolve(struct brw_context *brw,
-                           struct intel_mipmap_tree *mt,
-                           uint32_t level,
-                           uint32_t layer,
-                           enum blorp_hiz_op need)
+intel_miptree_depth_hiz_resolve(struct brw_context *brw,
+                                struct intel_mipmap_tree *mt,
+                                uint32_t start_level, uint32_t num_levels,
+                                uint32_t start_layer, uint32_t num_layers,
+                                enum blorp_hiz_op need)
 {
-   intel_miptree_check_level_layer(mt, level, layer);
+   bool did_resolve = false;
 
-   struct intel_resolve_map *item =
-        intel_resolve_map_get(&mt->hiz_map, level, layer);
+   foreach_list_typed_safe(struct intel_resolve_map, map, link, &mt->hiz_map) {
+      if (map->level < start_level ||
+          map->level >= (start_level + num_levels) ||
+          map->layer < start_layer ||
+          map->layer >= (start_layer + num_layers))
+         continue;
 
-   if (!item || item->need != need)
-      return false;
+      if (map->need != need)
+         continue;
 
-   intel_hiz_exec(brw, mt, level, layer, need);
-   intel_resolve_map_remove(item);
-   return true;
+      intel_hiz_exec(brw, mt, map->level, map->layer, 1, need);
+      intel_resolve_map_remove(map);
+      did_resolve = true;
+   }
+
+   return did_resolve;
 }
 
 bool
@@ -2002,8 +2009,8 @@ intel_miptree_slice_resolve_hiz(struct brw_context *brw,
                                uint32_t level,
                                uint32_t layer)
 {
-   return intel_miptree_slice_resolve(brw, mt, level, layer,
-                                     BLORP_HIZ_OP_HIZ_RESOLVE);
+   return intel_miptree_depth_hiz_resolve(brw, mt, level, 1, layer, 1,
+                                          BLORP_HIZ_OP_HIZ_RESOLVE);
 }
 
 bool
@@ -2012,43 +2019,26 @@ intel_miptree_slice_resolve_depth(struct brw_context *brw,
                                  uint32_t level,
                                  uint32_t layer)
 {
-   return intel_miptree_slice_resolve(brw, mt, level, layer,
-                                     BLORP_HIZ_OP_DEPTH_RESOLVE);
-}
-
-static bool
-intel_miptree_all_slices_resolve(struct brw_context *brw,
-                                struct intel_mipmap_tree *mt,
-                                enum blorp_hiz_op need)
-{
-   bool did_resolve = false;
-
-   foreach_list_typed_safe(struct intel_resolve_map, map, link, &mt->hiz_map) {
-      if (map->need != need)
-        continue;
-
-      intel_hiz_exec(brw, mt, map->level, map->layer, need);
-      intel_resolve_map_remove(map);
-      did_resolve = true;
-   }
-
-   return did_resolve;
+   return intel_miptree_depth_hiz_resolve(brw, mt, level, 1, layer, 1,
+                                          BLORP_HIZ_OP_DEPTH_RESOLVE);
 }
 
 bool
 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
                                     struct intel_mipmap_tree *mt)
 {
-   return intel_miptree_all_slices_resolve(brw, mt,
-                                          BLORP_HIZ_OP_HIZ_RESOLVE);
+   return intel_miptree_depth_hiz_resolve(brw, mt,
+                                          0, UINT32_MAX, 0, UINT32_MAX,
+                                          BLORP_HIZ_OP_HIZ_RESOLVE);
 }
 
 bool
 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
                                       struct intel_mipmap_tree *mt)
 {
-   return intel_miptree_all_slices_resolve(brw, mt,
-                                          BLORP_HIZ_OP_DEPTH_RESOLVE);
+   return intel_miptree_depth_hiz_resolve(brw, mt,
+                                          0, UINT32_MAX, 0, UINT32_MAX,
+                                          BLORP_HIZ_OP_DEPTH_RESOLVE);
 }
 
 enum intel_fast_clear_state
@@ -2174,33 +2164,48 @@ intel_miptree_needs_color_resolve(const struct brw_context *brw,
 
 bool
 intel_miptree_resolve_color(struct brw_context *brw,
-                            struct intel_mipmap_tree *mt, unsigned level,
-                            unsigned start_layer, unsigned num_layers,
+                            struct intel_mipmap_tree *mt,
+                            uint32_t start_level, uint32_t num_levels,
+                            uint32_t start_layer, uint32_t num_layers,
                             int flags)
 {
-   intel_miptree_check_color_resolve(brw, mt, level, start_layer);
+   intel_miptree_check_color_resolve(brw, mt, start_level, start_layer);
 
    if (!intel_miptree_needs_color_resolve(brw, mt, flags))
       return false;
 
-   /* Arrayed fast clear is only supported for gen8+. */
-   assert(brw->gen >= 8 || num_layers == 1);
+   enum blorp_fast_clear_op resolve_op;
+   if (brw->gen >= 9) {
+      if (intel_miptree_is_lossless_compressed(brw, mt)) {
+         resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+      } else {
+         resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+      }
+   } else {
+      /* Broadwell and earlier do not have a partial resolve */
+      assert(!intel_miptree_is_lossless_compressed(brw, mt));
+      resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+   }
 
    bool resolved = false;
-   for (unsigned i = 0; i < num_layers; ++i) {
-      intel_miptree_check_level_layer(mt, level, start_layer + i);
+   foreach_list_typed_safe(struct intel_resolve_map, map, link,
+                           &mt->color_resolve_map) {
+      if (map->level < start_level ||
+          map->level >= (start_level + num_levels) ||
+          map->layer < start_layer ||
+          map->layer >= (start_layer + num_layers))
+         continue;
 
-      struct intel_resolve_map *item =
-         intel_resolve_map_get(&mt->color_resolve_map, level,
-                               start_layer + i);
+      /* Arrayed and mip-mapped fast clear is only supported for gen8+. */
+      assert(brw->gen >= 8 || (map->level == 0 && map->layer == 0));
 
-      if (item) {
-         assert(item->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
+      intel_miptree_check_level_layer(mt, map->level, map->layer);
 
-         brw_blorp_resolve_color(brw, mt, level, start_layer);
-         intel_resolve_map_remove(item);
-         resolved = true;
-      }
+      assert(map->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
+
+      brw_blorp_resolve_color(brw, mt, map->level, map->layer, resolve_op);
+      intel_resolve_map_remove(map);
+      resolved = true;
    }
 
    return resolved;
@@ -2211,15 +2216,342 @@ intel_miptree_all_slices_resolve_color(struct brw_context *brw,
                                        struct intel_mipmap_tree *mt,
                                        int flags)
 {
-   if (!intel_miptree_needs_color_resolve(brw, mt, flags))
-      return;
-      
-   foreach_list_typed_safe(struct intel_resolve_map, map, link,
-                           &mt->color_resolve_map) {
-      assert(map->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
 
-      brw_blorp_resolve_color(brw, mt, map->level, map->layer);
-      intel_resolve_map_remove(map);
+   intel_miptree_resolve_color(brw, mt, 0, UINT32_MAX, 0, UINT32_MAX, flags);
+}
+
+static inline uint32_t
+miptree_level_range_length(const struct intel_mipmap_tree *mt,
+                           uint32_t start_level, uint32_t num_levels)
+{
+   assert(start_level >= mt->first_level);
+   assert(start_level <= mt->last_level);
+
+   if (num_levels == INTEL_REMAINING_LAYERS)
+      num_levels = mt->last_level - start_level + 1;
+   /* Check for overflow */
+   assert(start_level + num_levels >= start_level);
+   assert(start_level + num_levels <= mt->last_level + 1);
+
+   return num_levels;
+}
+
+static inline uint32_t
+miptree_layer_range_length(const struct intel_mipmap_tree *mt, uint32_t level,
+                           uint32_t start_layer, uint32_t num_layers)
+{
+   assert(level <= mt->last_level);
+   uint32_t total_num_layers = mt->level[level].depth;
+
+   assert(start_layer < total_num_layers);
+   if (num_layers == INTEL_REMAINING_LAYERS)
+      num_layers = total_num_layers - start_layer;
+   /* Check for overflow */
+   assert(start_layer + num_layers >= start_layer);
+   assert(start_layer + num_layers <= total_num_layers);
+
+   return num_layers;
+}
+
+void
+intel_miptree_prepare_access(struct brw_context *brw,
+                             struct intel_mipmap_tree *mt,
+                             uint32_t start_level, uint32_t num_levels,
+                             uint32_t start_layer, uint32_t num_layers,
+                             bool aux_supported, bool fast_clear_supported)
+{
+   num_levels = miptree_level_range_length(mt, start_level, num_levels);
+
+   if (_mesa_is_format_color_format(mt->format)) {
+      if (!mt->mcs_buf)
+         return;
+
+      if (mt->num_samples > 1) {
+         /* Nothing to do for MSAA */
+      } else {
+         /* TODO: This is fairly terrible.  We can do better. */
+         if (!aux_supported || !fast_clear_supported) {
+            intel_miptree_resolve_color(brw, mt, start_level, num_levels,
+                                        start_layer, num_layers, 0);
+         }
+      }
+   } else if (mt->format == MESA_FORMAT_S_UINT8) {
+      /* Nothing to do for stencil */
+   } else {
+      if (!mt->hiz_buf)
+         return;
+
+      if (aux_supported) {
+         assert(fast_clear_supported);
+         intel_miptree_depth_hiz_resolve(brw, mt, start_level, num_levels,
+                                         start_layer, num_layers,
+                                         BLORP_HIZ_OP_HIZ_RESOLVE);
+      } else {
+         assert(!fast_clear_supported);
+         intel_miptree_depth_hiz_resolve(brw, mt, start_level, num_levels,
+                                         start_layer, num_layers,
+                                         BLORP_HIZ_OP_DEPTH_RESOLVE);
+      }
+   }
+}
+
+void
+intel_miptree_finish_write(struct brw_context *brw,
+                           struct intel_mipmap_tree *mt, uint32_t level,
+                           uint32_t start_layer, uint32_t num_layers,
+                           bool written_with_aux)
+{
+   num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
+
+   if (_mesa_is_format_color_format(mt->format)) {
+      if (mt->num_samples > 1) {
+         /* Nothing to do for MSAA */
+      } else {
+         if (written_with_aux) {
+            intel_miptree_used_for_rendering(brw, mt, level,
+                                             start_layer, num_layers);
+         }
+      }
+   } else if (mt->format == MESA_FORMAT_S_UINT8) {
+      /* Nothing to do for stencil */
+   } else {
+      if (written_with_aux) {
+         for (unsigned a = 0; a < num_layers; a++) {
+            intel_miptree_check_level_layer(mt, level, start_layer);
+            intel_miptree_slice_set_needs_depth_resolve(mt, level,
+                                                        start_layer + a);
+         }
+      } else {
+         for (unsigned a = 0; a < num_layers; a++) {
+            intel_miptree_check_level_layer(mt, level, start_layer);
+            intel_miptree_slice_set_needs_hiz_resolve(mt, level,
+                                                      start_layer + a);
+         }
+      }
+   }
+}
+
+enum isl_aux_state
+intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
+                            uint32_t level, uint32_t layer)
+{
+   if (_mesa_is_format_color_format(mt->format)) {
+      assert(mt->mcs_buf != NULL);
+      if (mt->num_samples > 1) {
+         return ISL_AUX_STATE_COMPRESSED_CLEAR;
+      } else {
+         switch (intel_miptree_get_fast_clear_state(mt, level, layer)) {
+         case INTEL_FAST_CLEAR_STATE_RESOLVED:
+            return ISL_AUX_STATE_RESOLVED;
+         case INTEL_FAST_CLEAR_STATE_UNRESOLVED:
+            return ISL_AUX_STATE_COMPRESSED_CLEAR;
+         case INTEL_FAST_CLEAR_STATE_CLEAR:
+            return ISL_AUX_STATE_CLEAR;
+         default:
+            unreachable("Invalid fast clear state");
+         }
+      }
+   } else if (mt->format == MESA_FORMAT_S_UINT8) {
+      unreachable("Cannot get aux state for stencil");
+   } else {
+      assert(mt->hiz_buf != NULL);
+      const struct intel_resolve_map *map =
+         intel_resolve_map_const_get(&mt->hiz_map, level, layer);
+      if (!map)
+         return ISL_AUX_STATE_RESOLVED;
+      switch (map->need) {
+      case BLORP_HIZ_OP_DEPTH_RESOLVE:
+         return ISL_AUX_STATE_COMPRESSED_CLEAR;
+      case BLORP_HIZ_OP_HIZ_RESOLVE:
+         return ISL_AUX_STATE_AUX_INVALID;
+      default:
+         unreachable("Invalid hiz op");
+      }
+   }
+}
+
+void
+intel_miptree_set_aux_state(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t num_layers,
+                            enum isl_aux_state aux_state)
+{
+   num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
+
+   /* Right now, this only applies to clears. */
+   assert(aux_state == ISL_AUX_STATE_CLEAR);
+
+   if (_mesa_is_format_color_format(mt->format)) {
+      if (mt->num_samples > 1)
+         assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+
+      assert(level == 0 && start_layer == 0 && num_layers == 1);
+      intel_miptree_set_fast_clear_state(brw, mt, 0, 0, 1,
+                                         INTEL_FAST_CLEAR_STATE_CLEAR);
+   } else if (mt->format == MESA_FORMAT_S_UINT8) {
+      assert(!"Cannot set aux state for stencil");
+   } else {
+      for (unsigned a = 0; a < num_layers; a++) {
+         intel_miptree_check_level_layer(mt, level, start_layer);
+         intel_miptree_slice_set_needs_depth_resolve(mt, level,
+                                                     start_layer + a);
+      }
+   }
+}
+
+/* On Gen9 color buffers may be compressed by the hardware (lossless
+ * compression). There are, however, format restrictions and care needs to be
+ * taken that the sampler engine is capable for re-interpreting a buffer with
+ * format different the buffer was originally written with.
+ *
+ * For example, SRGB formats are not compressible and the sampler engine isn't
+ * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
+ * color buffer needs to be resolved so that the sampling surface can be
+ * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
+ * set).
+ */
+static bool
+intel_texture_view_requires_resolve(struct brw_context *brw,
+                                    struct intel_mipmap_tree *mt,
+                                    mesa_format format)
+{
+   if (brw->gen < 9 ||
+       !intel_miptree_is_lossless_compressed(brw, mt))
+     return false;
+
+   const enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
+
+   if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format))
+      return false;
+
+   perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
+              _mesa_get_format_name(format),
+              _mesa_get_format_name(mt->format));
+
+   return true;
+}
+
+static void
+intel_miptree_prepare_texture_slices(struct brw_context *brw,
+                                     struct intel_mipmap_tree *mt,
+                                     mesa_format view_format,
+                                     uint32_t start_level, uint32_t num_levels,
+                                     uint32_t start_layer, uint32_t num_layers,
+                                     bool *aux_supported_out)
+{
+   bool aux_supported;
+   if (_mesa_is_format_color_format(mt->format)) {
+      aux_supported = intel_miptree_is_lossless_compressed(brw, mt) &&
+                      !intel_texture_view_requires_resolve(brw, mt, view_format);
+   } else if (mt->format == MESA_FORMAT_S_UINT8) {
+      aux_supported = false;
+   } else {
+      aux_supported = intel_miptree_sample_with_hiz(brw, mt);
+   }
+
+   intel_miptree_prepare_access(brw, mt, start_level, num_levels,
+                                start_layer, num_layers,
+                                aux_supported, aux_supported);
+   if (aux_supported_out)
+      *aux_supported_out = aux_supported;
+}
+
+void
+intel_miptree_prepare_texture(struct brw_context *brw,
+                              struct intel_mipmap_tree *mt,
+                              mesa_format view_format,
+                              bool *aux_supported_out)
+{
+   intel_miptree_prepare_texture_slices(brw, mt, view_format,
+                                        0, INTEL_REMAINING_LEVELS,
+                                        0, INTEL_REMAINING_LAYERS,
+                                        aux_supported_out);
+}
+
+void
+intel_miptree_prepare_image(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt)
+{
+   /* The data port doesn't understand any compression */
+   intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
+                                0, INTEL_REMAINING_LAYERS, false, false);
+}
+
+void
+intel_miptree_prepare_fb_fetch(struct brw_context *brw,
+                               struct intel_mipmap_tree *mt, uint32_t level,
+                               uint32_t start_layer, uint32_t num_layers)
+{
+   intel_miptree_prepare_texture_slices(brw, mt, mt->format, level, 1,
+                                        start_layer, num_layers, NULL);
+}
+
+void
+intel_miptree_prepare_render(struct brw_context *brw,
+                             struct intel_mipmap_tree *mt, uint32_t level,
+                             uint32_t start_layer, uint32_t layer_count,
+                             bool srgb_enabled)
+{
+   /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
+    * the single-sampled color renderbuffers because the CCS buffer isn't
+    * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
+    * enabled because otherwise the surface state will be programmed with
+    * the linear equivalent format anyway.
+    */
+   if (brw->gen >= 9 && srgb_enabled && mt->num_samples <= 1 &&
+       _mesa_get_srgb_format_linear(mt->format) != mt->format) {
+
+      /* Lossless compression is not supported for SRGB formats, it
+       * should be impossible to get here with such surfaces.
+       */
+      assert(!intel_miptree_is_lossless_compressed(brw, mt));
+      intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                   false, false);
+   }
+
+   /* For layered rendering non-compressed fast cleared buffers need to be
+    * resolved. Surface state can carry only one fast color clear value
+    * while each layer may have its own fast clear color value. For
+    * compressed buffers color value is available in the color buffer.
+    */
+   if (layer_count > 1 &&
+       !(mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
+       !intel_miptree_is_lossless_compressed(brw, mt)) {
+      assert(brw->gen >= 8);
+
+      intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                   false, false);
+   }
+}
+
+void
+intel_miptree_finish_render(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t layer_count)
+{
+   assert(_mesa_is_format_color_format(mt->format));
+   intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
+                              mt->mcs_buf != NULL);
+}
+
+void
+intel_miptree_prepare_depth(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t layer_count)
+{
+   intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                mt->hiz_buf != NULL, mt->hiz_buf != NULL);
+}
+
+void
+intel_miptree_finish_depth(struct brw_context *brw,
+                           struct intel_mipmap_tree *mt, uint32_t level,
+                           uint32_t start_layer, uint32_t layer_count,
+                           bool depth_written)
+{
+   if (depth_written) {
+      intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
+                                 mt->hiz_buf != NULL);
    }
 }
 
@@ -2244,8 +2576,10 @@ intel_miptree_make_shareable(struct brw_context *brw,
     */
    assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE || mt->num_samples <= 1);
 
+   intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
+                                0, INTEL_REMAINING_LAYERS, false, false);
+
    if (mt->mcs_buf) {
-      intel_miptree_all_slices_resolve_color(brw, mt, 0);
       mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
       brw_bo_unreference(mt->mcs_buf->bo);
       free(mt->mcs_buf);
@@ -2260,7 +2594,6 @@ intel_miptree_make_shareable(struct brw_context *brw,
 
    if (mt->hiz_buf) {
       mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
-      intel_miptree_all_slices_resolve_depth(brw, mt);
       intel_miptree_hiz_buffer_free(mt->hiz_buf);
       mt->hiz_buf = NULL;
 
@@ -2416,32 +2749,12 @@ intel_miptree_map_raw(struct brw_context *brw,
                       struct intel_mipmap_tree *mt,
                       GLbitfield mode)
 {
-   /* CPU accesses to color buffers don't understand fast color clears, so
-    * resolve any pending fast color clears before we map.
-    */
-   intel_miptree_all_slices_resolve_color(brw, mt, 0);
-
    struct brw_bo *bo = mt->bo;
 
    if (brw_batch_references(&brw->batch, bo))
       intel_batchbuffer_flush(brw);
 
-   /* brw_bo_map_cpu() uses a WB mmaping of the buffer's backing storage. It
-    * will utilize the CPU cache even if the buffer is incoherent with the
-    * GPU (i.e. any writes will be stored in the cache and not flushed to
-    * memory and so will be invisible to the GPU or display engine). This
-    * is the majority of buffers on a !llc machine, but even on a llc
-    * almost all scanouts are incoherent with the CPU. A WB write into the
-    * backing storage of the current scanout will not be immediately
-    * visible on the screen. The transfer from cache to screen is slow and
-    * indeterministic causing visible glitching on the screen. Never use
-    * this WB mapping for writes to an active scanout (reads are fine, so
-    * long as cache consistency is maintained).
-    */
-   if (mt->tiling != I915_TILING_NONE || mt->is_scanout)
-      return brw_bo_map_gtt(brw, bo, mode);
-   else
-      return brw_bo_map_cpu(brw, bo, mode);
+   return brw_bo_map(brw, bo, mode);
 }
 
 static void
@@ -3038,10 +3351,8 @@ intel_miptree_map(struct brw_context *brw,
       return;
    }
 
-   intel_miptree_slice_resolve_depth(brw, mt, level, slice);
-   if (map->mode & GL_MAP_WRITE_BIT) {
-      intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice);
-   }
+   intel_miptree_access_raw(brw, mt, level, slice,
+                            map->mode & GL_MAP_WRITE_BIT);
 
    if (mt->format == MESA_FORMAT_S_UINT8) {
       intel_miptree_map_s8(brw, mt, map, level, slice);
@@ -3414,34 +3725,3 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
    surf->array_pitch_el_rows =
       aux_qpitch / isl_format_get_layout(surf->format)->bh;
 }
-
-union isl_color_value
-intel_miptree_get_isl_clear_color(struct brw_context *brw,
-                                  const struct intel_mipmap_tree *mt)
-{
-   union isl_color_value clear_color;
-
-   if (_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT) {
-      clear_color.i32[0] = mt->depth_clear_value;
-      clear_color.i32[1] = 0;
-      clear_color.i32[2] = 0;
-      clear_color.i32[3] = 0;
-   } else if (brw->gen >= 9) {
-      clear_color.i32[0] = mt->gen9_fast_clear_color.i[0];
-      clear_color.i32[1] = mt->gen9_fast_clear_color.i[1];
-      clear_color.i32[2] = mt->gen9_fast_clear_color.i[2];
-      clear_color.i32[3] = mt->gen9_fast_clear_color.i[3];
-   } else if (_mesa_is_format_integer(mt->format)) {
-      clear_color.i32[0] = (mt->fast_clear_color_value & (1u << 31)) != 0;
-      clear_color.i32[1] = (mt->fast_clear_color_value & (1u << 30)) != 0;
-      clear_color.i32[2] = (mt->fast_clear_color_value & (1u << 29)) != 0;
-      clear_color.i32[3] = (mt->fast_clear_color_value & (1u << 28)) != 0;
-   } else {
-      clear_color.f32[0] = (mt->fast_clear_color_value & (1u << 31)) != 0;
-      clear_color.f32[1] = (mt->fast_clear_color_value & (1u << 30)) != 0;
-      clear_color.f32[2] = (mt->fast_clear_color_value & (1u << 29)) != 0;
-      clear_color.f32[3] = (mt->fast_clear_color_value & (1u << 28)) != 0;
-   }
-
-   return clear_color;
-}