if (brw->gen >= 9) {
mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
const uint32_t brw_format = brw_format_for_mesa_format(linear_format);
- return brw_losslessly_compressible_format(brw, brw_format);
+ return isl_format_supports_lossless_compression(brw->intelScreen->devinfo,
+ brw_format);
} else
return true;
}
} else if (brw->gen >= 9 && num_samples > 1) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else {
- const bool is_lossless_compressed_aux =
+ const UNUSED bool is_lossless_compressed_aux =
brw->gen >= 9 && num_samples == 1 &&
mt->format == MESA_FORMAT_R_UINT32;
/* If this miptree is capable of supporting fast color clears, set
* fast_clear_state appropriately to ensure that fast clears will occur.
* Allocation of the MCS miptree will be deferred until the first fast
- * clear actually occurs.
+ * clear actually occurs or when compressed single sampled buffer is
+ * written by the GPU for the first time.
*/
if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
intel_miptree_release(&(*mt)->mcs_mt);
intel_resolve_map_clear(&(*mt)->hiz_map);
+ intel_miptree_release(&(*mt)->plane[0]);
+ intel_miptree_release(&(*mt)->plane[1]);
+
for (i = 0; i < MAX_TEXTURE_LEVELS; i++) {
free((*mt)->level[i].slice);
}
unsigned mcs_height =
ALIGN(mt->logical_height0, height_divisor) / height_divisor;
assert(mt->logical_depth0 == 1);
- uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_TILING_Y;
+ uint32_t layout_flags = MIPTREE_LAYOUT_TILING_Y;
+
if (brw->gen >= 8) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
}
+
+ /* On Gen9+ clients are not currently capable of consuming compressed
+ * single-sampled buffers. Disabling compression allows us to skip
+ * resolves.
+ */
+ const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
+ const bool is_lossless_compressed =
+ unlikely(!lossless_compression_disabled) &&
+ brw->gen >= 9 && !mt->is_scanout &&
+ intel_miptree_supports_lossless_compressed(brw, mt);
+
+ /* In case of compression mcs buffer needs to be initialised requiring the
+ * buffer to be immediately mapped to cpu space for writing. Therefore do
+ * not use the gpu access flag which can cause an unnecessary delay if the
+ * backing pages happened to be just used by the GPU.
+ */
+ if (!is_lossless_compressed)
+ layout_flags |= MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
+
mt->mcs_mt = miptree_create(brw,
mt->target,
format,
0 /* num_samples */,
layout_flags);
+ /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
+ * used for lossless compression which requires similar initialisation
+ * as multi-sample compression.
+ */
+ if (is_lossless_compressed) {
+ /* Hardware sets the auxiliary buffer to all zeroes when it does full
+ * resolve. Initialize it accordingly in case the first renderer is
+ * cpu (or other none compression aware party).
+ *
+ * This is also explicitly stated in the spec (MCS Buffer for Render
+ * Target(s)):
+ * "If Software wants to enable Color Compression without Fast clear,
+ * Software needs to initialize MCS with zeros."
+ */
+ intel_miptree_init_mcs(brw, mt, 0);
+ mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
+ mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+ }
+
return mt->mcs_mt;
}
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst)
{
- /* There is support for only up to eight samples. */
- const bool use_blorp = src->num_samples <= 8 && dst->num_samples <= 8;
-
- if (use_blorp) {
- brw_blorp_blit_miptrees(brw,
- src, 0 /* level */, 0 /* layer */,
- src->format, SWIZZLE_XYZW,
- dst, 0 /* level */, 0 /* layer */, dst->format,
- 0, 0,
- src->logical_width0, src->logical_height0,
- 0, 0,
- dst->logical_width0, dst->logical_height0,
- GL_NEAREST, false, false /*mirror x, y*/,
- false, false);
- } else if (src->format == MESA_FORMAT_S_UINT8) {
- brw_meta_stencil_updownsample(brw, src, dst);
- } else {
- brw_meta_updownsample(brw, src, dst);
- }
+ brw_blorp_blit_miptrees(brw,
+ src, 0 /* level */, 0 /* layer */,
+ src->format, SWIZZLE_XYZW,
+ dst, 0 /* level */, 0 /* layer */, dst->format,
+ 0, 0,
+ src->logical_width0, src->logical_height0,
+ 0, 0,
+ dst->logical_width0, dst->logical_height0,
+ GL_NEAREST, false, false /*mirror x, y*/,
+ false, false);
if (src->stencil_mt) {
- if (!use_blorp) {
- brw_meta_stencil_updownsample(brw, src->stencil_mt, dst);
- return;
- }
-
brw_blorp_blit_miptrees(brw,
src->stencil_mt, 0 /* level */, 0 /* layer */,
src->stencil_mt->format, SWIZZLE_XYZW,
intel_miptree_release_map(mt, level, slice);
}
+
+void
+intel_miptree_get_isl_surf(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ struct isl_surf *surf)
+{
+ switch (mt->target) {
+ case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D_ARRAY: {
+ surf->dim = ISL_SURF_DIM_1D;
+ if (brw->gen >= 9 && mt->tiling == I915_TILING_NONE)
+ surf->dim_layout = ISL_DIM_LAYOUT_GEN9_1D;
+ else
+ surf->dim_layout = ISL_DIM_LAYOUT_GEN4_2D;
+ break;
+ }
+ case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_RECTANGLE:
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
+ case GL_TEXTURE_EXTERNAL_OES:
+ surf->dim = ISL_SURF_DIM_2D;
+ surf->dim_layout = ISL_DIM_LAYOUT_GEN4_2D;
+ break;
+ case GL_TEXTURE_3D:
+ surf->dim = ISL_SURF_DIM_3D;
+ if (brw->gen >= 9)
+ surf->dim_layout = ISL_DIM_LAYOUT_GEN4_2D;
+ else
+ surf->dim_layout = ISL_DIM_LAYOUT_GEN4_3D;
+ break;
+ default:
+ unreachable("Invalid texture target");
+ }
+
+ if (mt->num_samples > 1) {
+ switch (mt->msaa_layout) {
+ case INTEL_MSAA_LAYOUT_IMS:
+ surf->msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
+ break;
+ case INTEL_MSAA_LAYOUT_UMS:
+ case INTEL_MSAA_LAYOUT_CMS:
+ surf->msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
+ break;
+ default:
+ unreachable("Invalid MSAA layout");
+ }
+ } else {
+ surf->msaa_layout = ISL_MSAA_LAYOUT_NONE;
+ }
+
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ surf->tiling = ISL_TILING_W;
+ /* The ISL definition of row_pitch matches the surface state pitch field
+ * a bit better than intel_mipmap_tree. In particular, ISL incorporates
+ * the factor of 2 for W-tiling in row_pitch.
+ */
+ surf->row_pitch = 2 * mt->pitch;
+ } else {
+ switch (mt->tiling) {
+ case I915_TILING_NONE:
+ surf->tiling = ISL_TILING_LINEAR;
+ break;
+ case I915_TILING_X:
+ surf->tiling = ISL_TILING_X;
+ break;
+ case I915_TILING_Y:
+ switch (mt->tr_mode) {
+ case INTEL_MIPTREE_TRMODE_NONE:
+ surf->tiling = ISL_TILING_Y0;
+ break;
+ case INTEL_MIPTREE_TRMODE_YF:
+ surf->tiling = ISL_TILING_Yf;
+ break;
+ case INTEL_MIPTREE_TRMODE_YS:
+ surf->tiling = ISL_TILING_Ys;
+ break;
+ }
+ break;
+ default:
+ unreachable("Invalid tiling mode");
+ }
+
+ surf->row_pitch = mt->pitch;
+ }
+
+ surf->format = translate_tex_format(brw, mt->format, false);
+
+ if (brw->gen >= 9) {
+ if (surf->dim == ISL_SURF_DIM_1D && surf->tiling == ISL_TILING_LINEAR) {
+ /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
+ surf->image_alignment_el = isl_extent3d(64, 1, 1);
+ } else {
+ /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
+ * alignment in terms of surface elements like we want.
+ */
+ surf->image_alignment_el = isl_extent3d(mt->halign, mt->valign, 1);
+ }
+ } else {
+ /* On earlier gens it's stored in pixels. */
+ unsigned bw, bh;
+ _mesa_get_format_block_size(mt->format, &bw, &bh);
+ surf->image_alignment_el =
+ isl_extent3d(mt->halign / bw, mt->valign / bh, 1);
+ }
+
+ surf->logical_level0_px.width = mt->logical_width0;
+ surf->logical_level0_px.height = mt->logical_height0;
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ surf->logical_level0_px.depth = mt->logical_depth0;
+ surf->logical_level0_px.array_len = 1;
+ } else if (mt->target == GL_TEXTURE_CUBE_MAP ||
+ mt->target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ /* For cube maps, mt->logical_depth0 is in number of cubes */
+ surf->logical_level0_px.depth = 1;
+ surf->logical_level0_px.array_len = mt->logical_depth0 * 6;
+ } else {
+ surf->logical_level0_px.depth = 1;
+ surf->logical_level0_px.array_len = mt->logical_depth0;
+ }
+
+ surf->phys_level0_sa.width = mt->physical_width0;
+ surf->phys_level0_sa.height = mt->physical_height0;
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ surf->phys_level0_sa.depth = mt->physical_depth0;
+ surf->phys_level0_sa.array_len = 1;
+ } else {
+ surf->phys_level0_sa.depth = 1;
+ surf->phys_level0_sa.array_len = mt->physical_depth0;
+ }
+
+ surf->levels = mt->last_level + 1;
+ surf->samples = MAX2(mt->num_samples, 1);
+
+ surf->size = 0; /* TODO */
+ surf->alignment = 0; /* TODO */
+
+ switch (surf->dim_layout) {
+ case ISL_DIM_LAYOUT_GEN4_2D:
+ case ISL_DIM_LAYOUT_GEN4_3D:
+ if (brw->gen >= 9) {
+ surf->array_pitch_el_rows = mt->qpitch;
+ } else {
+ unsigned bw, bh;
+ _mesa_get_format_block_size(mt->format, &bw, &bh);
+ assert(mt->qpitch % bh == 0);
+ surf->array_pitch_el_rows = mt->qpitch / bh;
+ }
+ break;
+ case ISL_DIM_LAYOUT_GEN9_1D:
+ surf->array_pitch_el_rows = 1;
+ break;
+ }
+
+ switch (mt->array_layout) {
+ case ALL_LOD_IN_EACH_SLICE:
+ surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_FULL;
+ break;
+ case ALL_SLICES_AT_EACH_LOD:
+ surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_COMPACT;
+ break;
+ default:
+ unreachable("Invalid array layout");
+ }
+
+ surf->usage = 0; /* TODO */
+}
projects / mesa.git / blobdiff