}
static bool
-need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
+need_to_retile_as_linear(struct brw_context *brw, unsigned blt_pitch,
enum isl_tiling tiling, unsigned samples)
{
if (samples > 1)
if (tiling == ISL_TILING_LINEAR)
return false;
- /* If the width is much smaller than a tile, don't bother tiling. */
- if (row_pitch < 64)
- return true;
-
- if (ALIGN(row_pitch, 512) >= 32768) {
- perf_debug("row pitch %u too large to blit, falling back to untiled",
- row_pitch);
+ if (blt_pitch >= 32768) {
+ perf_debug("blt pitch %u too large to blit, falling back to untiled",
+ blt_pitch);
return true;
}
unsigned width0, unsigned height0, unsigned depth0,
unsigned num_samples, isl_tiling_flags_t tiling_flags,
isl_surf_usage_flags_t isl_usage_flags, uint32_t alloc_flags,
- unsigned row_pitch, struct brw_bo *bo)
+ unsigned row_pitch_B, struct brw_bo *bo)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
.levels = last_level - first_level + 1,
.array_len = target == GL_TEXTURE_3D ? 1 : depth0,
.samples = num_samples,
- .row_pitch = row_pitch,
+ .row_pitch_B = row_pitch_B,
.usage = isl_usage_flags,
.tiling_flags = tiling_flags,
};
bool is_depth_stencil =
mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
if (!is_depth_stencil) {
- if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
+ if (need_to_retile_as_linear(brw, intel_miptree_blt_pitch(mt),
mt->surf.tiling, mt->surf.samples)) {
init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
- } else if (need_to_retile_as_x(brw, mt->surf.size, mt->surf.tiling)) {
+ } else if (need_to_retile_as_x(brw, mt->surf.size_B, mt->surf.tiling)) {
init_info.tiling_flags = 1u << ISL_TILING_X;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
* See isl_apply_surface_padding().
*/
if (mt->surf.tiling != ISL_TILING_LINEAR)
- assert(mt->surf.size % mt->surf.row_pitch == 0);
+ assert(mt->surf.size_B % mt->surf.row_pitch_B == 0);
if (!bo) {
mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
- mt->surf.size,
+ mt->surf.size_B,
BRW_MEMZONE_OTHER,
isl_tiling_to_i915_tiling(
mt->surf.tiling),
- mt->surf.row_pitch, alloc_flags);
+ mt->surf.row_pitch_B, alloc_flags);
if (!mt->bo)
goto fail;
} else {
return NULL;
}
-static bool
-make_separate_stencil_surface(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+/* Return the usual surface usage flags for the given format. */
+static isl_surf_usage_flags_t
+mt_surf_usage(mesa_format format)
{
- mt->stencil_mt = make_surface(brw, mt->target, MESA_FORMAT_S_UINT8,
- 0, mt->surf.levels - 1,
- mt->surf.logical_level0_px.width,
- mt->surf.logical_level0_px.height,
- mt->surf.dim == ISL_SURF_DIM_3D ?
- mt->surf.logical_level0_px.depth :
- mt->surf.logical_level0_px.array_len,
- mt->surf.samples, ISL_TILING_W_BIT,
- ISL_SURF_USAGE_STENCIL_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY, 0, NULL);
-
- if (!mt->stencil_mt)
- return false;
-
- mt->stencil_mt->r8stencil_needs_update = true;
-
- return true;
+ switch(_mesa_get_format_base_format(format)) {
+ case GL_DEPTH_COMPONENT:
+ return ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ case GL_DEPTH_STENCIL:
+ return ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT;
+ case GL_STENCIL_INDEX:
+ return ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ default:
+ return ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ }
}
static struct intel_mipmap_tree *
enum intel_miptree_create_flags flags)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const uint32_t alloc_flags =
+ (flags & MIPTREE_CREATE_BUSY || num_samples > 1) ? BO_ALLOC_BUSY : 0;
+ isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
- if (format == MESA_FORMAT_S_UINT8)
- return make_surface(brw, target, format, first_level, last_level,
- width0, height0, depth0, num_samples,
- ISL_TILING_W_BIT,
- ISL_SURF_USAGE_STENCIL_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY,
- 0,
- NULL);
+ /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
+ if (devinfo->gen < 6 && _mesa_is_format_color_format(format))
+ tiling_flags &= ~ISL_TILING_Y0_BIT;
- const GLenum base_format = _mesa_get_format_base_format(format);
- if ((base_format == GL_DEPTH_COMPONENT ||
- base_format == GL_DEPTH_STENCIL) &&
- !(flags & MIPTREE_CREATE_LINEAR)) {
+ mesa_format mt_fmt;
+ if (_mesa_is_format_color_format(format)) {
+ mt_fmt = intel_lower_compressed_format(brw, format);
+ } else {
/* Fix up the Z miptree format for how we're splitting out separate
- * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
+ * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
*/
- const mesa_format depth_only_format =
- intel_depth_format_for_depthstencil_format(format);
- struct intel_mipmap_tree *mt = make_surface(
- brw, target, devinfo->gen >= 6 ? depth_only_format : format,
- first_level, last_level,
- width0, height0, depth0, num_samples, ISL_TILING_Y0_BIT,
- ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY, 0, NULL);
-
- if (needs_separate_stencil(brw, mt, format) &&
- !make_separate_stencil_surface(brw, mt)) {
- intel_miptree_release(&mt);
- return NULL;
- }
-
- if (!(flags & MIPTREE_CREATE_NO_AUX))
- intel_miptree_choose_aux_usage(brw, mt);
-
- return mt;
+ mt_fmt = (devinfo->gen < 6) ? format :
+ intel_depth_format_for_depthstencil_format(format);
}
- mesa_format tex_format = format;
- mesa_format etc_format = MESA_FORMAT_NONE;
- uint32_t alloc_flags = 0;
-
- format = intel_lower_compressed_format(brw, format);
-
- etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
-
- if (flags & MIPTREE_CREATE_BUSY)
- alloc_flags |= BO_ALLOC_BUSY;
-
- isl_tiling_flags_t tiling_flags = (flags & MIPTREE_CREATE_LINEAR) ?
- ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
-
- /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
- if (devinfo->gen < 6)
- tiling_flags &= ~ISL_TILING_Y0_BIT;
+ struct intel_mipmap_tree *mt =
+ make_surface(brw, target, mt_fmt, first_level, last_level,
+ width0, height0, depth0, num_samples,
+ tiling_flags, mt_surf_usage(mt_fmt),
+ alloc_flags, 0, NULL);
- struct intel_mipmap_tree *mt = make_surface(
- brw, target, format,
- first_level, last_level,
- width0, height0, depth0,
- num_samples, tiling_flags,
- ISL_SURF_USAGE_RENDER_TARGET_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
- alloc_flags, 0, NULL);
- if (!mt)
+ if (mt == NULL)
return NULL;
- mt->etc_format = etc_format;
+ if (needs_separate_stencil(brw, mt, format)) {
+ mt->stencil_mt =
+ make_surface(brw, target, MESA_FORMAT_S_UINT8, first_level, last_level,
+ width0, height0, depth0, num_samples,
+ ISL_TILING_W_BIT, mt_surf_usage(MESA_FORMAT_S_UINT8),
+ alloc_flags, 0, NULL);
+ if (mt->stencil_mt == NULL) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
+
+ mt->etc_format = (_mesa_is_format_color_format(format) && mt_fmt != format) ?
+ format : MESA_FORMAT_NONE;
if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
if ((base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL)) {
- const mesa_format depth_only_format =
+ const mesa_format mt_fmt = (devinfo->gen < 6) ? format :
intel_depth_format_for_depthstencil_format(format);
- mt = make_surface(brw, target,
- devinfo->gen >= 6 ? depth_only_format : format,
+ mt = make_surface(brw, target, mt_fmt,
0, 0, width, height, depth, 1, ISL_TILING_Y0_BIT,
- ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
+ mt_surf_usage(mt_fmt),
0, pitch, bo);
if (!mt)
return NULL;
mt = make_surface(brw, target, MESA_FORMAT_S_UINT8,
0, 0, width, height, depth, 1,
ISL_TILING_W_BIT,
- ISL_SURF_USAGE_STENCIL_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
+ mt_surf_usage(MESA_FORMAT_S_UINT8),
0, pitch, bo);
if (!mt)
return NULL;
- assert(bo->size >= mt->surf.size);
+ assert(bo->size >= mt->surf.size_B);
brw_bo_reference(bo);
return mt;
*/
assert(pitch >= 0);
- /* The BO already has a tiling format and we shouldn't confuse the lower
- * layers by making it try to find a tiling format again.
- */
- assert((flags & MIPTREE_CREATE_LINEAR) == 0);
-
mt = make_surface(brw, target, format,
0, 0, width, height, depth, 1,
1lu << tiling,
- ISL_SURF_USAGE_RENDER_TARGET_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
+ mt_surf_usage(format),
0, pitch, bo);
if (!mt)
return NULL;
image->strides[index],
tiling,
MIPTREE_CREATE_NO_AUX);
- if (mt == NULL)
+ if (mt == NULL) {
+ intel_miptree_release(&planar_mt);
return NULL;
+ }
mt->target = target;
return false;
assert(image->aux_offset < image->bo->size);
- assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+ assert(temp_ccs_surf.size_B <= image->bo->size - image->aux_offset);
mt->aux_buf = calloc(sizeof(*mt->aux_buf), 1);
if (mt->aux_buf == NULL)
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
mesa_format format,
- bool is_winsys_image)
+ bool allow_internal_aux)
{
uint32_t bo_tiling, bo_swizzle;
brw_bo_get_tiling(image->bo, &bo_tiling, &bo_swizzle);
* other hand, have no resolve point so we can't have aux without a
* modifier.
*/
- if (!is_winsys_image)
+ if (!allow_internal_aux)
mt_create_flags |= MIPTREE_CREATE_NO_AUX;
/* If we have a modifier which specifies aux, don't create one yet */
* as part of the flush operation.
*/
mt->supports_fast_clear =
- is_winsys_image || mod_info->supports_clear_color;
+ allow_internal_aux || mod_info->supports_clear_color;
/* We don't know the actual state of the surface when we get it but we
* can make a pretty good guess based on the modifier. What we do know
uint32_t x, uint32_t y)
{
int cpp = mt->cpp;
- uint32_t pitch = mt->surf.row_pitch;
+ uint32_t pitch = mt->surf.row_pitch_B;
switch (mt->surf.tiling) {
default:
unsigned dst_level, unsigned dst_layer)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
mesa_format format = src_mt->format;
unsigned width = minify(src_mt->surf.phys_level0_sa.width,
src_level - src_mt->first_level);
assert(_mesa_get_srgb_format_linear(src_mt->format) ==
_mesa_get_srgb_format_linear(dst_mt->format));
+ DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
+ _mesa_get_format_name(src_mt->format),
+ src_mt, src_level, src_layer,
+ _mesa_get_format_name(dst_mt->format),
+ dst_mt, dst_level, dst_layer,
+ width, height);
+
+ if (devinfo->gen >= 6) {
+ /* On gen6 and above, we just use blorp. It's faster than the blitter
+ * and can handle everything without software fallbacks.
+ */
+ brw_blorp_copy_miptrees(brw,
+ src_mt, src_level, src_layer,
+ dst_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+
+ if (src_mt->stencil_mt) {
+ assert(dst_mt->stencil_mt);
+ brw_blorp_copy_miptrees(brw,
+ src_mt->stencil_mt, src_level, src_layer,
+ dst_mt->stencil_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+ }
+ return;
+ }
+
if (dst_mt->compressed) {
unsigned int i, j;
_mesa_get_format_block_size(dst_mt->format, &i, &j);
width = ALIGN_NPOT(width, i) / i;
}
- /* If it's a packed depth/stencil buffer with separate stencil, the blit
- * below won't apply since we can't do the depth's Y tiling or the
- * stencil's W tiling in the blitter.
- */
- if (src_mt->stencil_mt) {
- intel_miptree_copy_slice_sw(brw,
- src_mt, src_level, src_layer,
- dst_mt, dst_level, dst_layer,
- width, height);
- return;
- }
+ /* Gen4-5 doesn't support separate stencil */
+ assert(!src_mt->stencil_mt);
uint32_t dst_x, dst_y, src_x, src_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_layer,
DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
_mesa_get_format_name(src_mt->format),
- src_mt, src_x, src_y, src_mt->surf.row_pitch,
+ src_mt, src_x, src_y, src_mt->surf.row_pitch_B,
_mesa_get_format_name(dst_mt->format),
- dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch,
+ dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch_B,
width, height);
if (!intel_miptree_blit(brw,
if (!buf)
return false;
- uint64_t size = aux_surf->size;
+ uint64_t size = aux_surf->size_B;
const bool has_indirect_clear = brw->isl_dev.ss.clear_color_state_size > 0;
if (has_indirect_clear) {
*/
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "aux-miptree", size,
BRW_MEMZONE_OTHER, I915_TILING_Y,
- aux_surf->row_pitch, alloc_flags);
+ aux_surf->row_pitch_B, alloc_flags);
if (!buf->bo) {
free(buf);
return NULL;
/* Memset the aux_surf portion of the BO. */
if (wants_memset)
- memset(map, memset_value, aux_surf->size);
+ memset(map, memset_value, aux_surf->size_B);
/* Zero the indirect clear color to match ::fast_clear_color. */
if (has_indirect_clear) {
const struct gen_device_info *devinfo = &brw->screen->devinfo;
assert(mt->aux_buf);
- assert(mt->surf.size > 0);
+ assert(mt->surf.size_B > 0);
if (devinfo->gen >= 8 || devinfo->is_haswell) {
uint32_t width = minify(mt->surf.phys_level0_sa.width, level);
enum isl_aux_state initial_state;
uint8_t memset_value;
struct isl_surf aux_surf;
- MAYBE_UNUSED bool aux_surf_ok;
+ MAYBE_UNUSED bool aux_surf_ok = false;
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
- aux_surf.size = 0;
+ aux_surf.size_B = 0;
aux_surf_ok = true;
break;
case ISL_AUX_USAGE_HIZ:
initial_state = ISL_AUX_STATE_AUX_INVALID;
+ memset_value = 0;
aux_surf_ok = isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &aux_surf);
break;
case ISL_AUX_USAGE_MCS:
assert(aux_surf_ok);
/* No work is needed for a zero-sized auxiliary buffer. */
- if (aux_surf.size == 0)
+ if (aux_surf.size_B == 0)
return true;
/* Create the aux_state for the auxiliary buffer. */
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_usage aux_usage)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
- /* Nothing to do */
+ if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7)
+ mt->r8stencil_needs_update = true;
break;
case ISL_AUX_USAGE_MCS:
enum isl_aux_usage
intel_miptree_texture_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- enum isl_format view_format)
+ enum isl_format view_format,
+ enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
{
+ assert(brw->screen->devinfo.gen == 9 || astc5x5_wa_bits == 0);
+
+ /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
+ * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
+ * details.
+ */
+ if ((astc5x5_wa_bits & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
+ mt->aux_usage != ISL_AUX_USAGE_MCS)
+ return ISL_AUX_USAGE_NONE;
+
switch (mt->aux_usage) {
case ISL_AUX_USAGE_HIZ:
if (intel_miptree_sample_with_hiz(brw, mt))
struct intel_mipmap_tree *mt,
enum isl_format view_format,
uint32_t start_level, uint32_t num_levels,
- uint32_t start_layer, uint32_t num_layers)
+ uint32_t start_layer, uint32_t num_layers,
+ enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
{
enum isl_aux_usage aux_usage =
- intel_miptree_texture_aux_usage(brw, mt, view_format);
+ intel_miptree_texture_aux_usage(brw, mt, view_format, astc5x5_wa_bits);
+
bool clear_supported = aux_usage != ISL_AUX_USAGE_NONE;
/* Clear color is specified as ints or floats and the conversion is done by
{
if (depth_written) {
intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
- mt->aux_buf != NULL);
+ mt->aux_usage);
}
}
assert(devinfo->gen >= 7);
struct intel_mipmap_tree *src =
mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt;
- if (!src || devinfo->gen >= 8 || !src->r8stencil_needs_update)
+ if (!src || devinfo->gen >= 8)
return;
- assert(src->surf.size > 0);
+ assert(src->surf.size_B > 0);
if (!mt->r8stencil_mt) {
assert(devinfo->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
assert(mt->r8stencil_mt);
}
+ if (src->r8stencil_needs_update == false)
+ return;
+
struct intel_mipmap_tree *dst = mt->r8stencil_mt;
for (int level = src->first_level; level <= src->last_level; level++) {
y /= bh;
x /= bw;
+ intel_miptree_access_raw(brw, mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
+
base = intel_miptree_map_raw(brw, mt, map->mode);
if (base == NULL)
x += image_x;
y += image_y;
- map->stride = mt->surf.row_pitch;
+ map->stride = mt->surf.row_pitch_B;
map->ptr = base + y * map->stride + x * mt->cpp;
}
unsigned int level,
unsigned int slice)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
intel_miptree_unmap_raw(map->linear_mt);
if (map->mode & GL_MAP_WRITE_BIT) {
- bool ok = intel_miptree_copy(brw,
- map->linear_mt, 0, 0, 0, 0,
- mt, level, slice, map->x, map->y,
- map->w, map->h);
- WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+ if (devinfo->gen >= 6) {
+ brw_blorp_copy_miptrees(brw, map->linear_mt, 0, 0,
+ mt, level, slice,
+ 0, 0, map->x, map->y, map->w, map->h);
+ } else {
+ bool ok = intel_miptree_copy(brw,
+ map->linear_mt, 0, 0, 0, 0,
+ mt, level, slice, map->x, map->y,
+ map->w, map->h);
+ WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+ }
}
intel_miptree_release(&map->linear_mt);
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
{
- map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
- /* first_level */ 0,
- /* last_level */ 0,
- map->w, map->h, 1,
- /* samples */ 1,
- MIPTREE_CREATE_LINEAR);
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ map->linear_mt = make_surface(brw, GL_TEXTURE_2D, mt->format,
+ 0, 0, map->w, map->h, 1, 1,
+ ISL_TILING_LINEAR_BIT,
+ ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ 0, 0, NULL);
if (!map->linear_mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
goto fail;
}
- map->stride = map->linear_mt->surf.row_pitch;
+ map->stride = map->linear_mt->surf.row_pitch_B;
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* temporary buffer back out.
*/
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
- if (!intel_miptree_copy(brw,
- mt, level, slice, map->x, map->y,
- map->linear_mt, 0, 0, 0, 0,
- map->w, map->h)) {
- fprintf(stderr, "Failed to blit\n");
- goto fail;
+ if (devinfo->gen >= 6) {
+ brw_blorp_copy_miptrees(brw, mt, level, slice,
+ map->linear_mt, 0, 0,
+ map->x, map->y, 0, 0, map->w, map->h);
+ } else {
+ if (!intel_miptree_copy(brw,
+ mt, level, slice, map->x, map->y,
+ map->linear_mt, 0, 0, 0, 0,
+ map->w, map->h)) {
+ fprintf(stderr, "Failed to blit\n");
+ goto fail;
+ }
}
}
assert(map->mode & GL_MAP_READ_BIT);
assert(!(map->mode & GL_MAP_WRITE_BIT));
+ intel_miptree_access_raw(brw, mt, level, slice, false);
+
DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
mt, _mesa_get_format_name(mt->format),
src += mt->offset;
- src += image_y * mt->surf.row_pitch;
+ src += image_y * mt->surf.row_pitch_B;
src += image_x * mt->cpp;
/* Due to the pixel offsets for the particular image being mapped, our
* divisible by 16, then the amount by which it's misaligned will remain
* consistent from row to row.
*/
- assert((mt->surf.row_pitch % 16) == 0);
+ assert((mt->surf.row_pitch_B % 16) == 0);
const int misalignment = ((uintptr_t) src) & 15;
/* Create an untiled temporary buffer for the mapping. */
for (uint32_t y = 0; y < map->h; y++) {
void *dst_ptr = map->ptr + y * map->stride;
- void *src_ptr = src + y * mt->surf.row_pitch;
+ void *src_ptr = src + y * mt->surf.row_pitch_B;
_mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes);
}
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch,
+ ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch_B,
image_x + x + map->x,
image_y + y + map->y,
brw->has_swizzling);
if (!map->buffer)
return;
+ intel_miptree_access_raw(brw, mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
+
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* invalidate is set, since we'll be writing the whole rectangle from our
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch,
+ ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch_B,
x + image_x + map->x,
y + image_y + map->y,
brw->has_swizzling);
image_y += map->y;
uint8_t *dst = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT)
- + image_y * mt->surf.row_pitch
+ + image_y * mt->surf.row_pitch_B
+ image_x * mt->cpp;
if (mt->etc_format == MESA_FORMAT_ETC1_RGB8)
- _mesa_etc1_unpack_rgba8888(dst, mt->surf.row_pitch,
+ _mesa_etc1_unpack_rgba8888(dst, mt->surf.row_pitch_B,
map->ptr, map->stride,
map->w, map->h);
else
- _mesa_unpack_etc2_format(dst, mt->surf.row_pitch,
+ _mesa_unpack_etc2_format(dst, mt->surf.row_pitch_B,
map->ptr, map->stride,
- map->w, map->h, mt->etc_format);
+ map->w, map->h, mt->etc_format, true);
intel_miptree_unmap_raw(mt);
free(map->buffer);
assert(map->mode & GL_MAP_WRITE_BIT);
assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
+ intel_miptree_access_raw(brw, mt, level, slice, true);
+
map->stride = _mesa_format_row_stride(mt->etc_format, map->w);
map->buffer = malloc(_mesa_format_image_size(mt->etc_format,
map->w, map->h, 1));
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch_B,
x + s_image_x + map->x,
y + s_image_y + map->y,
brw->has_swizzling);
ptrdiff_t z_offset = ((y + z_image_y + map->y) *
- (z_mt->surf.row_pitch / 4) +
+ (z_mt->surf.row_pitch_B / 4) +
(x + z_image_x + map->x));
if (map_z32f_x24s8) {
if (!map->buffer)
return;
+ intel_miptree_access_raw(brw, z_mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
+ intel_miptree_access_raw(brw, s_mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
+
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* invalidate is set, since we'll be writing the whole rectangle from our
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
int map_x = map->x + x, map_y = map->y + y;
- ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch_B,
map_x + s_image_x,
map_y + s_image_y,
brw->has_swizzling);
ptrdiff_t z_offset = ((map_y + z_image_y) *
- (z_mt->surf.row_pitch / 4) +
+ (z_mt->surf.row_pitch_B / 4) +
(map_x + z_image_x));
uint8_t s = s_map[s_offset];
uint32_t z = z_map[z_offset];
static bool
can_blit_slice(struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int slice)
+ const struct intel_miptree_map *map)
{
/* See intel_miptree_blit() for details on the 32k pitch limit. */
- if (mt->surf.row_pitch >= 32768)
- return false;
-
- return true;
+ const unsigned src_blt_pitch = intel_miptree_blt_pitch(mt);
+ const unsigned dst_blt_pitch = ALIGN(map->w * mt->cpp, 64);
+ return src_blt_pitch < 32768 && dst_blt_pitch < 32768;
}
static bool
use_intel_mipree_map_blit(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- GLbitfield mode,
- unsigned int level,
- unsigned int slice)
+ const struct intel_miptree_map *map)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
/* It's probably not worth swapping to the blit ring because of
* all the overhead involved.
*/
- !(mode & GL_MAP_WRITE_BIT) &&
+ !(map->mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
(mt->surf.tiling == ISL_TILING_X ||
/* Prior to Sandybridge, the blitter can't handle Y tiling */
(devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) ||
/* Fast copy blit on skl+ supports all tiling formats. */
devinfo->gen >= 9) &&
- can_blit_slice(mt, level, slice))
+ can_blit_slice(mt, map))
return true;
if (mt->surf.tiling != ISL_TILING_LINEAR &&
mt->bo->size >= brw->max_gtt_map_object_size) {
- assert(can_blit_slice(mt, level, slice));
+ assert(can_blit_slice(mt, map));
return true;
}
return;
}
- intel_miptree_access_raw(brw, mt, level, slice,
- map->mode & GL_MAP_WRITE_BIT);
-
if (mt->format == MESA_FORMAT_S_UINT8) {
intel_miptree_map_s8(brw, mt, map, level, slice);
} else if (mt->etc_format != MESA_FORMAT_NONE &&
intel_miptree_map_etc(brw, mt, map, level, slice);
} else if (mt->stencil_mt && !(mode & BRW_MAP_DIRECT_BIT)) {
intel_miptree_map_depthstencil(brw, mt, map, level, slice);
- } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
+ } else if (use_intel_mipree_map_blit(brw, mt, map)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
#if defined(USE_SSE41)
} else if (!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed && cpu_has_sse4_1 &&
- (mt->surf.row_pitch % 16 == 0)) {
+ (mt->surf.row_pitch_B % 16 == 0)) {
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {
projects / mesa.git / blobdiff