free(state);
}
+static struct intel_mipmap_tree *
+make_surface(struct brw_context *brw, GLenum target, mesa_format format,
+ unsigned first_level, unsigned last_level,
+ unsigned width0, unsigned height0, unsigned depth0,
+ unsigned num_samples, enum isl_tiling isl_tiling,
+ isl_surf_usage_flags_t isl_usage_flags, uint32_t alloc_flags,
+ struct brw_bo *bo)
+{
+ struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
+ if (!mt)
+ return NULL;
+
+ if (!create_mapping_table(target, first_level, last_level, depth0,
+ mt->level)) {
+ free(mt);
+ return NULL;
+ }
+
+ if (target == GL_TEXTURE_CUBE_MAP ||
+ target == GL_TEXTURE_CUBE_MAP_ARRAY)
+ isl_usage_flags |= ISL_SURF_USAGE_CUBE_BIT;
+
+ DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
+ __func__,
+ _mesa_enum_to_string(target),
+ _mesa_get_format_name(format),
+ num_samples, width0, height0, depth0,
+ first_level, last_level, mt);
+
+ struct isl_surf_init_info init_info = {
+ .dim = get_isl_surf_dim(target),
+ .format = translate_tex_format(brw, format, false),
+ .width = width0,
+ .height = height0,
+ .depth = target == GL_TEXTURE_3D ? depth0 : 1,
+ .levels = last_level - first_level + 1,
+ .array_len = target == GL_TEXTURE_3D ? 1 : depth0,
+ .samples = MAX2(num_samples, 1),
+ .usage = isl_usage_flags,
+ .tiling_flags = 1u << isl_tiling
+ };
+
+ if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
+ goto fail;
+
+ assert(mt->surf.size % mt->surf.row_pitch == 0);
+
+ if (!bo) {
+ mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
+ mt->surf.size,
+ isl_tiling_to_bufmgr_tiling(isl_tiling),
+ mt->surf.row_pitch, alloc_flags);
+ if (!mt->bo)
+ goto fail;
+ } else {
+ mt->bo = bo;
+ }
+
+ mt->first_level = first_level;
+ mt->last_level = last_level;
+ mt->target = target;
+ mt->format = format;
+ mt->refcount = 1;
+ mt->aux_state = NULL;
+
+ return mt;
+
+fail:
+ intel_miptree_release(&mt);
+ return NULL;
+}
+
static struct intel_mipmap_tree *
miptree_create(struct brw_context *brw,
GLenum target,
GLuint num_samples,
uint32_t layout_flags)
{
+ if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
+ return make_surface(brw, target, format, first_level, last_level,
+ width0, height0, depth0, num_samples, ISL_TILING_W,
+ ISL_SURF_USAGE_STENCIL_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ BO_ALLOC_FOR_RENDER, NULL);
+
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
mesa_format etc_format = MESA_FORMAT_NONE;
if (hiz_buf == NULL)
return;
- if (hiz_buf->mt)
- intel_miptree_release(&hiz_buf->mt);
- else
- brw_bo_unreference(hiz_buf->aux_base.bo);
+ brw_bo_unreference(hiz_buf->aux_base.bo);
free(hiz_buf);
}
GLuint level, GLuint slice,
GLuint *x, GLuint *y)
{
+ if (mt->surf.size > 0) {
+ uint32_t x_offset_sa, y_offset_sa;
+
+ /* Given level is relative to level zero while the miptree may be
+ * represent just a subset of all levels starting from 'first_level'.
+ */
+ assert(level >= mt->first_level);
+ level -= mt->first_level;
+
+ const unsigned z = mt->surf.dim == ISL_SURF_DIM_3D ? slice : 0;
+ slice = mt->surf.dim == ISL_SURF_DIM_3D ? 0 : slice;
+ isl_surf_get_image_offset_sa(&mt->surf, level, slice, z,
+ &x_offset_sa, &y_offset_sa);
+
+ *x = x_offset_sa;
+ *y = y_offset_sa;
+ return;
+ }
+
assert(slice < mt->level[level].depth);
*x = mt->level[level].slice[slice].x_offset;
{
void *src, *dst;
ptrdiff_t src_stride, dst_stride;
- int cpp = dst_mt->cpp;
+ const unsigned cpp = dst_mt->surf.size > 0 ?
+ (isl_format_get_layout(dst_mt->surf.format)->bpb / 8) : dst_mt->cpp;
intel_miptree_map(brw, src_mt,
src_level, src_layer,
unsigned dst_level, unsigned dst_layer)
{
- uint32_t width = minify(src_mt->physical_width0,
- src_level - src_mt->first_level);
- uint32_t height = minify(src_mt->physical_height0,
- src_level - src_mt->first_level);
mesa_format format = src_mt->format;
+ uint32_t width, height;
+
+ if (src_mt->surf.size > 0) {
+ width = minify(src_mt->surf.phys_level0_sa.width,
+ src_level - src_mt->first_level);
+ height = minify(src_mt->surf.phys_level0_sa.height,
+ src_level - src_mt->first_level);
+
+ if (src_mt->surf.dim == ISL_SURF_DIM_3D)
+ assert(src_layer < minify(src_mt->surf.phys_level0_sa.depth,
+ src_level - src_mt->first_level));
+ else
+ assert(src_layer < src_mt->surf.phys_level0_sa.array_len);
+ } else {
+ width = minify(src_mt->physical_width0,
+ src_level - src_mt->first_level);
+ height = minify(src_mt->physical_height0,
+ src_level - src_mt->first_level);
+ assert(src_layer < src_mt->level[src_level].depth);
+ }
- assert(src_layer < src_mt->level[src_level].depth);
assert(src_mt->format == dst_mt->format);
if (dst_mt->compressed) {
}
static struct intel_miptree_aux_buffer *
-intel_mcs_miptree_buf_create(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- mesa_format format,
- unsigned mcs_width,
- unsigned mcs_height,
- uint32_t layout_flags)
+intel_alloc_aux_buffer(struct brw_context *brw,
+ const char *name,
+ const struct isl_surf *aux_surf,
+ uint32_t alloc_flags,
+ struct intel_mipmap_tree *mt)
{
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
- struct intel_mipmap_tree *temp_mt;
-
if (!buf)
- return NULL;
+ return false;
- /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
- *
- * "The MCS surface must be stored as Tile Y."
+ buf->size = aux_surf->size;
+ buf->pitch = aux_surf->row_pitch;
+ buf->qpitch = isl_surf_get_array_pitch_sa_rows(aux_surf);
+
+ /* ISL has stricter set of alignment rules then the drm allocator.
+ * Therefore one can pass the ISL dimensions in terms of bytes instead of
+ * trying to recalculate based on different format block sizes.
*/
- layout_flags |= MIPTREE_LAYOUT_TILING_Y;
- temp_mt = miptree_create(brw,
- mt->target,
- format,
- mt->first_level,
- mt->last_level,
- mcs_width,
- mcs_height,
- mt->logical_depth0,
- 0 /* num_samples */,
- layout_flags);
- if (!temp_mt) {
+ buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, buf->size,
+ I915_TILING_Y, buf->pitch, alloc_flags);
+ if (!buf->bo) {
free(buf);
return NULL;
}
- buf->bo = temp_mt->bo;
- buf->offset = temp_mt->offset;
- buf->size = temp_mt->total_height * temp_mt->pitch;
- buf->pitch = temp_mt->pitch;
- buf->qpitch = temp_mt->qpitch;
-
- /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
- * structure should go away. We use miptree create simply as a means to make
- * sure all the constraints for the buffer are satisfied.
- */
- brw_bo_reference(temp_mt->bo);
- intel_miptree_release(&temp_mt);
+ buf->surf = *aux_surf;
return buf;
}
assert(mt->mcs_buf == NULL);
assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
- /* Choose the correct format for the MCS buffer. All that really matters
- * is that we allocate the right buffer size, since we'll always be
- * accessing this miptree using MCS-specific hardware mechanisms, which
- * infer the correct format based on num_samples.
- */
- mesa_format format;
- switch (num_samples) {
- case 2:
- case 4:
- /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
- * each sample).
- */
- format = MESA_FORMAT_R_UNORM8;
- break;
- case 8:
- /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
- * for each sample, plus 8 padding bits).
- */
- format = MESA_FORMAT_R_UINT32;
- break;
- case 16:
- /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
- * for each sample).
- */
- format = MESA_FORMAT_RG_UINT32;
- break;
- default:
- unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
- };
-
/* Multisampled miptrees are only supported for single level. */
assert(mt->first_level == 0);
enum isl_aux_state **aux_state =
if (!aux_state)
return false;
- mt->mcs_buf =
- intel_mcs_miptree_buf_create(brw, mt,
- format,
- mt->logical_width0,
- mt->logical_height0,
- MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
+ struct isl_surf temp_main_surf;
+ struct isl_surf temp_mcs_surf;
+
+ /* Create first an ISL presentation for the main color surface and let ISL
+ * calculate equivalent MCS surface against it.
+ */
+ intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+ assert(isl_surf_get_mcs_surf(&brw->isl_dev, &temp_main_surf,
+ &temp_mcs_surf));
+
+ const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;
+ mt->mcs_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
+ &temp_mcs_surf, alloc_flags, mt);
if (!mt->mcs_buf) {
free(aux_state);
return false;
assert(temp_ccs_surf.size &&
(temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
- struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
- if (!buf)
- return false;
-
enum isl_aux_state **aux_state =
create_aux_state_map(mt, ISL_AUX_STATE_PASS_THROUGH);
- if (!aux_state) {
- free(buf);
+ if (!aux_state)
return false;
- }
-
- buf->size = temp_ccs_surf.size;
- buf->pitch = temp_ccs_surf.row_pitch;
- buf->qpitch = isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf);
/* In case of compression mcs buffer needs to be initialised requiring the
* buffer to be immediately mapped to cpu space for writing. Therefore do
*/
const uint32_t alloc_flags =
is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER;
-
- buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size,
- I915_TILING_Y, buf->pitch, alloc_flags);
- if (!buf->bo) {
- free(buf);
+ mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
+ &temp_ccs_surf, alloc_flags, mt);
+ if (!mt->mcs_buf) {
free(aux_state);
return false;
}
-
- mt->mcs_buf = buf;
+
mt->aux_state = aux_state;
/* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
struct intel_mipmap_tree *mt)
{
struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
- uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
-
- if (brw->gen == 6)
- layout_flags |= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL;
-
if (!buf)
return NULL;
- layout_flags |= MIPTREE_LAYOUT_TILING_ANY;
- buf->mt = intel_miptree_create(brw,
- mt->target,
- mt->format,
- mt->first_level,
- mt->last_level,
- mt->logical_width0,
- mt->logical_height0,
- mt->logical_depth0,
- mt->num_samples,
- layout_flags);
- if (!buf->mt) {
+ struct isl_surf temp_main_surf;
+ intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+
+ if (!isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf,
+ &buf->aux_base.surf)) {
free(buf);
return NULL;
}
- buf->aux_base.bo = buf->mt->bo;
- buf->aux_base.size = buf->mt->total_height * buf->mt->pitch;
- buf->aux_base.pitch = buf->mt->pitch;
- buf->aux_base.qpitch = buf->mt->qpitch * 2;
+ struct isl_surf *surf = &buf->aux_base.surf;
+ buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz", surf->size,
+ I915_TILING_Y, surf->row_pitch,
+ BO_ALLOC_FOR_RENDER);
+ if (!buf->aux_base.bo) {
+ free(buf);
+ return NULL;
+ }
return buf;
}
uint32_t start_layer, uint32_t num_layers)
{
assert(level <= mt->last_level);
- uint32_t total_num_layers = mt->level[level].depth;
+ uint32_t total_num_layers;
+
+ if (mt->surf.size > 0)
+ total_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
+ minify(mt->surf.phys_level0_sa.depth, level) :
+ mt->surf.phys_level0_sa.array_len;
+ else
+ total_num_layers = mt->level[level].depth;
assert(start_layer < total_num_layers);
if (num_layers == INTEL_REMAINING_LAYERS)
* temporary buffer back out.
*/
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
+ /* ISL uses a stencil pitch value that is expected by hardware whereas
+ * traditional miptree uses half of that. Below the value gets supplied
+ * to intel_offset_S8() which expects the legacy interpretation.
+ */
+ const unsigned pitch = mt->surf.size > 0 ?
+ mt->surf.row_pitch / 2 : mt->pitch;
uint8_t *untiled_s8_map = map->ptr;
uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt, GL_MAP_READ_BIT);
unsigned int image_x, image_y;
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->pitch,
+ ptrdiff_t offset = intel_offset_S8(pitch,
x + image_x + map->x,
y + image_y + map->y,
brw->has_swizzling);
unsigned int slice)
{
if (map->mode & GL_MAP_WRITE_BIT) {
+ /* ISL uses a stencil pitch value that is expected by hardware whereas
+ * traditional miptree uses half of that. Below the value gets supplied
+ * to intel_offset_S8() which expects the legacy interpretation.
+ */
+ const unsigned pitch = mt->surf.size > 0 ?
+ mt->surf.row_pitch / 2: mt->pitch;
unsigned int image_x, image_y;
uint8_t *untiled_s8_map = map->ptr;
uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->pitch,
+ ptrdiff_t offset = intel_offset_S8(pitch,
image_x + x + map->x,
image_y + y + map->y,
brw->has_swizzling);
* temporary buffer back out.
*/
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
+ /* ISL uses a stencil pitch value that is expected by hardware whereas
+ * traditional miptree uses half of that. Below the value gets supplied
+ * to intel_offset_S8() which expects the legacy interpretation.
+ */
+ const unsigned s_pitch = s_mt->surf.size > 0 ?
+ s_mt->surf.row_pitch / 2 : s_mt->pitch;
uint32_t *packed_map = map->ptr;
uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_READ_BIT);
uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_READ_BIT);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
int map_x = map->x + x, map_y = map->y + y;
- ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_pitch,
map_x + s_image_x,
map_y + s_image_y,
brw->has_swizzling);
bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
if (map->mode & GL_MAP_WRITE_BIT) {
+ /* ISL uses a stencil pitch value that is expected by hardware whereas
+ * traditional miptree uses half of that. Below the value gets supplied
+ * to intel_offset_S8() which expects the legacy interpretation.
+ */
+ const unsigned s_pitch = s_mt->surf.size > 0 ?
+ s_mt->surf.row_pitch / 2 : s_mt->pitch;
uint32_t *packed_map = map->ptr;
uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_WRITE_BIT);
uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_WRITE_BIT);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_pitch,
x + s_image_x + map->x,
y + s_image_y + map->y,
brw->has_swizzling);
surf->usage |= ISL_SURF_USAGE_CUBE_BIT;
}
+enum isl_aux_usage
+intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
+{
+ if (mt->hiz_buf)
+ return ISL_AUX_USAGE_HIZ;
+
+ if (!mt->mcs_buf)
+ return ISL_AUX_USAGE_NONE;
+
+ if (mt->num_samples > 1) {
+ assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+ return ISL_AUX_USAGE_MCS;
+ }
+
+ if (intel_miptree_is_lossless_compressed(brw, mt)) {
+ assert(brw->gen >= 9);
+ return ISL_AUX_USAGE_CCS_E;
+ }
+
+ if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0)
+ return ISL_AUX_USAGE_CCS_D;
+
+ unreachable("Invalid MCS miptree");
+}
+
/* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
* USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
* PASS IT INTO isl_surf_fill_state.
void
intel_miptree_get_aux_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct isl_surf *surf,
- enum isl_aux_usage *usage)
+ enum isl_aux_usage usage,
+ struct isl_surf *surf)
{
uint32_t aux_pitch, aux_qpitch;
if (mt->mcs_buf) {
aux_pitch = mt->mcs_buf->pitch;
aux_qpitch = mt->mcs_buf->qpitch;
-
- if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
- } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
- } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
- } else {
- unreachable("Invalid MCS miptree");
- }
} else if (mt->hiz_buf) {
aux_pitch = mt->hiz_buf->aux_base.pitch;
aux_qpitch = mt->hiz_buf->aux_base.qpitch;
-
- *usage = ISL_AUX_USAGE_HIZ;
} else {
- *usage = ISL_AUX_USAGE_NONE;
return;
}
intel_miptree_get_isl_surf(brw, mt, surf);
/* Figure out the format and tiling of the auxiliary surface */
- switch (*usage) {
+ switch (usage) {
case ISL_AUX_USAGE_NONE:
unreachable("Invalid auxiliary usage");
projects / mesa.git / blobdiff