intel_miptree_alloc_aux(struct brw_context *brw,
struct intel_mipmap_tree *mt);
-/**
- * Determine which MSAA layout should be used by the MSAA surface being
- * created, based on the chip generation and the surface type.
- */
-static enum intel_msaa_layout
-compute_msaa_layout(struct brw_context *brw, mesa_format format,
- uint32_t layout_flags)
+static bool
+is_mcs_supported(const struct brw_context *brw, mesa_format format,
+ uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
- return INTEL_MSAA_LAYOUT_IMS;
+ return false;
/* In Gen7, IMS layout is only used for depth and stencil buffers. */
switch (_mesa_get_format_base_format(format)) {
case GL_DEPTH_COMPONENT:
case GL_STENCIL_INDEX:
case GL_DEPTH_STENCIL:
- return INTEL_MSAA_LAYOUT_IMS;
+ return false;
default:
/* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
*
* which is expensive.
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
- return INTEL_MSAA_LAYOUT_UMS;
+ return false;
} else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
/* We can't use the CMS layout because it uses an aux buffer, the MCS
* buffer. So fallback to UMS, which is identical to CMS without the
* MCS. */
- return INTEL_MSAA_LAYOUT_UMS;
+ return false;
} else {
- return INTEL_MSAA_LAYOUT_CMS;
+ return true;
}
}
}
+/**
+ * Determine which MSAA layout should be used by the MSAA surface being
+ * created, based on the chip generation and the surface type.
+ */
+static enum isl_msaa_layout
+compute_msaa_layout(struct brw_context *brw, mesa_format format,
+ uint32_t layout_flags)
+{
+ /* Prior to Gen7, all MSAA surfaces used IMS layout. */
+ if (brw->gen < 7)
+ return ISL_MSAA_LAYOUT_INTERLEAVED;
+
+ /* In Gen7, IMS layout is only used for depth and stencil buffers. */
+ switch (_mesa_get_format_base_format(format)) {
+ case GL_DEPTH_COMPONENT:
+ case GL_STENCIL_INDEX:
+ case GL_DEPTH_STENCIL:
+ return ISL_MSAA_LAYOUT_INTERLEAVED;
+ default:
+ return ISL_MSAA_LAYOUT_ARRAY;
+ }
+}
+
static bool
-intel_tiling_supports_ccs(const struct brw_context *brw, unsigned tiling)
+intel_tiling_supports_ccs(const struct brw_context *brw,
+ enum isl_tiling tiling)
{
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
* Gen9 changes the restriction to Y-tile only.
*/
if (brw->gen >= 9)
- return tiling == I915_TILING_Y;
+ return tiling == ISL_TILING_Y0;
else if (brw->gen >= 7)
- return tiling != I915_TILING_NONE;
+ return tiling != ISL_TILING_LINEAR;
else
return false;
}
return false;
/* This function applies only to non-multisampled render targets. */
- if (mt->num_samples > 1)
+ if (mt->surf.samples > 1)
return false;
/* MCS is only supported for color buffers */
* accidentally reject a multisampled surface here. We should have
* rejected it earlier by explicitly checking the sample count.
*/
- assert(mt->num_samples <= 1);
+ assert(mt->surf.samples == 1);
}
/* Handle the hardware restrictions...
}
static bool
-intel_tiling_supports_hiz(const struct brw_context *brw, unsigned tiling)
+intel_tiling_supports_hiz(const struct brw_context *brw,
+ enum isl_tiling tiling)
{
if (brw->gen < 6)
return false;
- return tiling == I915_TILING_Y;
+ return tiling == ISL_TILING_Y0;
}
static bool
-intel_miptree_supports_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+intel_miptree_supports_hiz(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
{
if (!brw->has_hiz)
return false;
return false;
}
+static bool
+needs_separate_stencil(const struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ mesa_format format, uint32_t layout_flags)
+{
+
+ if (layout_flags & MIPTREE_LAYOUT_FOR_BO)
+ return false;
+
+ if (_mesa_get_format_base_format(format) != GL_DEPTH_STENCIL)
+ return false;
+
+ if (brw->must_use_separate_stencil)
+ return true;
+
+ return brw->has_separate_stencil &&
+ intel_miptree_supports_hiz(brw, mt);
+}
+
/**
* @param for_bo Indicates that the caller is
* intel_miptree_create_for_bo(). If true, then do not create
GLuint num_samples,
uint32_t layout_flags)
{
+ assert(num_samples > 0);
+
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
- mt->num_samples = num_samples;
+ mt->surf.samples = num_samples;
mt->compressed = _mesa_is_format_compressed(format);
- mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE;
+ mt->surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
mt->refcount = 1;
if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format, layout_flags);
- if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
+ mt->surf.msaa_layout = compute_msaa_layout(brw, format, layout_flags);
+ if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
* surface or Multisampled Surface StorageFormat in SURFACE_STATE is
if (brw->gen >= 9) {
mt->array_layout = ALL_LOD_IN_EACH_SLICE;
} else {
- switch (mt->msaa_layout) {
- case INTEL_MSAA_LAYOUT_NONE:
- case INTEL_MSAA_LAYOUT_IMS:
+ switch (mt->surf.msaa_layout) {
+ case ISL_MSAA_LAYOUT_NONE:
+ case ISL_MSAA_LAYOUT_INTERLEAVED:
mt->array_layout = ALL_LOD_IN_EACH_SLICE;
break;
- case INTEL_MSAA_LAYOUT_UMS:
- case INTEL_MSAA_LAYOUT_CMS:
+ case ISL_MSAA_LAYOUT_ARRAY:
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
break;
}
mt->physical_height0 = height0;
mt->physical_depth0 = depth0;
- if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
- _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
- (brw->must_use_separate_stencil ||
- (brw->has_separate_stencil && intel_miptree_supports_hiz(brw, mt)))) {
+ if (needs_separate_stencil(brw, mt, format, layout_flags)) {
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
* 6 | ? | ?
*/
if (intel_miptree_supports_ccs(brw, mt)) {
- if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1))
+ if (brw->gen >= 9 || (brw->gen == 8 && num_samples == 1))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else if (brw->gen >= 9 && num_samples > 1) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
{
assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
- if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ const unsigned no_flags = 0;
+ if (mt->surf.samples > 1 && is_mcs_supported(brw, mt->format, no_flags)) {
+ assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
mt->aux_usage = ISL_AUX_USAGE_MCS;
- } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
+ } else if (intel_tiling_supports_ccs(brw, mt->surf.tiling) &&
intel_miptree_supports_ccs(brw, mt)) {
if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
brw->gen >= 9 && !mt->is_scanout &&
} else {
mt->aux_usage = ISL_AUX_USAGE_CCS_D;
}
- } else if (intel_tiling_supports_hiz(brw, mt->tiling) &&
+ } else if (intel_tiling_supports_hiz(brw, mt->surf.tiling) &&
intel_miptree_supports_hiz(brw, mt)) {
mt->aux_usage = ISL_AUX_USAGE_HIZ;
}
make_surface(struct brw_context *brw, GLenum target, mesa_format format,
unsigned first_level, unsigned last_level,
unsigned width0, unsigned height0, unsigned depth0,
- unsigned num_samples, enum isl_tiling isl_tiling,
+ unsigned num_samples, isl_tiling_flags_t tiling_flags,
isl_surf_usage_flags_t isl_usage_flags, uint32_t alloc_flags,
- struct brw_bo *bo)
+ unsigned row_pitch, struct brw_bo *bo)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
}
+ mt->refcount = 1;
+
if (target == GL_TEXTURE_CUBE_MAP ||
target == GL_TEXTURE_CUBE_MAP_ARRAY)
isl_usage_flags |= ISL_SURF_USAGE_CUBE_BIT;
.depth = target == GL_TEXTURE_3D ? depth0 : 1,
.levels = last_level - first_level + 1,
.array_len = target == GL_TEXTURE_3D ? 1 : depth0,
- .samples = MAX2(num_samples, 1),
+ .samples = num_samples,
+ .row_pitch = row_pitch,
.usage = isl_usage_flags,
- .tiling_flags = 1u << isl_tiling
+ .tiling_flags = tiling_flags,
};
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
if (!bo) {
mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
mt->surf.size,
- isl_tiling_to_bufmgr_tiling(isl_tiling),
+ isl_tiling_to_i915_tiling(
+ mt->surf.tiling),
mt->surf.row_pitch, alloc_flags);
if (!mt->bo)
goto fail;
mt->last_level = last_level;
mt->target = target;
mt->format = format;
- mt->refcount = 1;
mt->aux_state = NULL;
return mt;
{
if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
return make_surface(brw, target, format, first_level, last_level,
- width0, height0, depth0, num_samples, ISL_TILING_W,
+ width0, height0, depth0, num_samples,
+ ISL_TILING_W_BIT,
ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, NULL);
+ BO_ALLOC_FOR_RENDER, 0, NULL);
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
if (!mt)
return NULL;
- if (mt->tiling == (I915_TILING_Y | I915_TILING_X))
- mt->tiling = I915_TILING_Y;
-
if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
alloc_flags |= BO_ALLOC_FOR_RENDER;
mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
ALIGN(mt->total_width, 64),
ALIGN(mt->total_height, 64),
- mt->cpp, mt->tiling, &mt->pitch,
+ mt->cpp,
+ isl_tiling_to_i915_tiling(
+ mt->surf.tiling),
+ &mt->pitch,
alloc_flags);
+
+ /* The stencil buffer has quirky pitch requirements. From the
+ * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
+ * dword 1 bits 16:0 - Surface Pitch):
+ *
+ * The pitch must be set to 2x the value computed based on width, as
+ * the stencil buffer is stored with two rows interleaved.
+ *
+ * While the Ivybridge PRM lacks this comment, the BSpec contains the
+ * same text, and experiments indicate that this is necessary.
+ */
+ mt->pitch *= 2;
} else {
mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
mt->total_width, mt->total_height,
- mt->cpp, mt->tiling, &mt->pitch,
+ mt->cpp,
+ isl_tiling_to_i915_tiling(
+ mt->surf.tiling),
+ &mt->pitch,
alloc_flags);
}
GLuint num_samples,
uint32_t layout_flags)
{
+ assert(num_samples > 0);
+
struct intel_mipmap_tree *mt = miptree_create(
brw, target, format,
first_level, last_level,
width0, height0, depth0, num_samples,
layout_flags);
+ if (!mt)
+ return NULL;
/* If the BO is too large to fit in the aperture, we need to use the
* BLT engine to support it. Prior to Sandybridge, the BLT paths can't
* handle Y-tiling, so we need to fall back to X.
*/
if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size &&
- mt->tiling == I915_TILING_Y) {
+ mt->surf.tiling == ISL_TILING_Y0) {
const uint32_t alloc_flags =
(layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ?
BO_ALLOC_FOR_RENDER : 0;
perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
mt->total_width, mt->total_height);
- mt->tiling = I915_TILING_X;
+ mt->surf.tiling = ISL_TILING_X;
brw_bo_unreference(mt->bo);
mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
mt->total_width, mt->total_height, mt->cpp,
- mt->tiling, &mt->pitch, alloc_flags);
+ isl_tiling_to_i915_tiling(
+ mt->surf.tiling),
+ &mt->pitch, alloc_flags);
}
mt->offset = 0;
if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8) {
mt = make_surface(brw, target, MESA_FORMAT_S_UINT8,
- 0, 0, width, height, depth, 1, ISL_TILING_W,
+ 0, 0, width, height, depth, 1,
+ ISL_TILING_W_BIT,
ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_FOR_RENDER, bo);
+ BO_ALLOC_FOR_RENDER, pitch, bo);
if (!mt)
return NULL;
layout_flags |= MIPTREE_LAYOUT_FOR_BO;
mt = intel_miptree_create_layout(brw, target, format,
0, 0,
- width, height, depth, 0,
+ width, height, depth,
+ 1 /* num_samples */,
layout_flags);
if (!mt)
return NULL;
mt->bo = bo;
mt->pitch = pitch;
mt->offset = offset;
- mt->tiling = tiling;
+ mt->surf.tiling = isl_tiling_from_i915_tiling(tiling);
if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return NULL;
mt->target = target;
- mt->total_width = width;
- mt->total_height = height;
if (i == 0)
planar_mt = mt;
mt->level[0].level_y = image->tile_y;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
- mt->total_width += image->tile_x;
- mt->total_height += image->tile_y;
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = &irb->Base.Base;
mesa_format format = rb->Format;
- int num_samples = rb->NumSamples;
+ const unsigned num_samples = MAX2(rb->NumSamples, 1);
/* Only the front and back buffers, which are color buffers, are allocated
* through the image loader.
assert(singlesample_mt);
- if (num_samples == 0) {
+ if (num_samples == 1) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
}
int level_depth = mt->level[level].depth;
- if (mt->num_samples > 1) {
- switch (mt->msaa_layout) {
- case INTEL_MSAA_LAYOUT_NONE:
- case INTEL_MSAA_LAYOUT_IMS:
- break;
- case INTEL_MSAA_LAYOUT_UMS:
- case INTEL_MSAA_LAYOUT_CMS:
- level_depth /= mt->num_samples;
- break;
- }
- }
+ if (mt->surf.samples > 1 && mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)
+ level_depth /= mt->surf.samples;
/* Test image dimensions against the base level image adjusted for
* minification. This will also catch images not present in the
return false;
}
- if (image->NumSamples != mt->num_samples)
+ /* Core uses sample number of zero to indicate single-sampled. */
+ if (MAX2(image->NumSamples, 1) != mt->surf.samples)
return false;
return true;
* and tile_h is set to 1.
*/
void
-intel_get_tile_dims(uint32_t tiling, uint32_t cpp,
+intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
uint32_t *tile_w, uint32_t *tile_h)
{
switch (tiling) {
- case I915_TILING_X:
+ case ISL_TILING_X:
*tile_w = 512;
*tile_h = 8;
break;
- case I915_TILING_Y:
+ case ISL_TILING_Y0:
*tile_w = 128;
*tile_h = 32;
break;
- case I915_TILING_NONE:
+ case ISL_TILING_LINEAR:
*tile_w = cpp;
*tile_h = 1;
break;
* untiled, the masks are set to 0.
*/
void
-intel_get_tile_masks(uint32_t tiling, uint32_t cpp,
+intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
uint32_t *mask_x, uint32_t *mask_y)
{
uint32_t tile_w_bytes, tile_h;
{
int cpp = mt->cpp;
uint32_t pitch = mt->pitch;
- uint32_t tiling = mt->tiling;
- switch (tiling) {
+ switch (mt->surf.tiling) {
default:
unreachable("not reached");
- case I915_TILING_NONE:
+ case ISL_TILING_LINEAR:
return y * pitch + x * cpp;
- case I915_TILING_X:
+ case ISL_TILING_X:
assert((x % (512 / cpp)) == 0);
assert((y % 8) == 0);
return y * pitch + x / (512 / cpp) * 4096;
- case I915_TILING_Y:
+ case ISL_TILING_Y0:
assert((x % (128 / cpp)) == 0);
assert((y % 32) == 0);
return y * pitch + x / (128 / cpp) * 4096;
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y);
+ intel_get_tile_masks(mt->surf.tiling, mt->cpp, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
* calculate equivalent CCS surface against it.
*/
intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
- if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf, &temp_ccs_surf))
+ if (!isl_surf_get_ccs_surf(&brw->isl_dev, &temp_main_surf,
+ &temp_ccs_surf, 0))
return false;
assert(temp_ccs_surf.size &&
if (!aux_state)
return false;
- /* In case of compression mcs buffer needs to be initialised requiring the
- * buffer to be immediately mapped to cpu space for writing. Therefore do
- * not use the gpu access flag which can cause an unnecessary delay if the
- * backing pages happened to be just used by the GPU.
+ /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
+ * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
+ *
+ * "If Software wants to enable Color Compression without Fast clear,
+ * Software needs to initialize MCS with zeros."
+ *
+ * A CCS value of 0 indicates that the corresponding block is in the
+ * pass-through state which is what we want.
+ *
+ * For CCS_D, on the other hand, we don't care as we're about to perform a
+ * fast-clear operation. In that case, being hot in caches more useful.
*/
- const uint32_t alloc_flags =
- mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER;
+ const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
+ BO_ALLOC_ZEROED : BO_ALLOC_FOR_RENDER;
mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
&temp_ccs_surf, alloc_flags, mt);
if (!mt->mcs_buf) {
mt->aux_state = aux_state;
- /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
- * used for lossless compression which requires similar initialisation
- * as multi-sample compression.
- */
- if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- /* Hardware sets the auxiliary buffer to all zeroes when it does full
- * resolve. Initialize it accordingly in case the first renderer is
- * cpu (or other none compression aware party).
- *
- * This is also explicitly stated in the spec (MCS Buffer for Render
- * Target(s)):
- * "If Software wants to enable Color Compression without Fast clear,
- * Software needs to initialize MCS with zeros."
- */
- intel_miptree_init_mcs(brw, mt, 0);
- }
-
return true;
}
case ISL_AUX_USAGE_MCS:
assert(_mesa_is_format_color_format(mt->format));
- assert(mt->num_samples > 1);
- if (!intel_miptree_alloc_mcs(brw, mt, mt->num_samples))
+ assert(mt->surf.samples > 1);
+ if (!intel_miptree_alloc_mcs(brw, mt, mt->surf.samples))
return false;
return true;
case ISL_AUX_USAGE_CCS_E:
assert(_mesa_is_format_color_format(mt->format));
- assert(mt->num_samples <= 1);
+ assert(mt->surf.samples == 1);
if (!intel_miptree_alloc_ccs(brw, mt))
return false;
return true;
* There is no such blurb for 1D textures, but there is sufficient evidence
* that this is broken on SKL+.
*/
- return (mt->num_samples <= 1 &&
+ return (mt->surf.samples == 1 &&
mt->target != GL_TEXTURE_3D &&
mt->target != GL_TEXTURE_1D /* gen9+ restriction */);
}
(level == 0 && mt->first_level == 0 && mt->last_level == 0));
/* Compression of arrayed msaa surfaces is supported. */
- if (mt->num_samples > 1)
+ if (mt->surf.samples > 1)
return;
/* Fast color clear is supported for non-msaa arrays only on Gen8+. */
if (!mt->mcs_buf)
return;
- if (mt->num_samples > 1) {
+ if (mt->surf.samples > 1) {
/* Nothing to do for MSAA */
assert(aux_supported && fast_clear_supported);
} else {
if (!mt->mcs_buf)
return;
- if (mt->num_samples > 1) {
+ if (mt->surf.samples > 1) {
for (uint32_t a = 0; a < num_layers; a++) {
intel_miptree_finish_mcs_write(brw, mt, level, start_layer + a,
written_with_aux);
if (_mesa_is_format_color_format(mt->format)) {
assert(mt->mcs_buf != NULL);
- assert(mt->num_samples <= 1 || mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+ assert(mt->surf.samples == 1 ||
+ mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
unreachable("Cannot get aux state for stencil");
} else {
if (_mesa_is_format_color_format(mt->format)) {
assert(mt->mcs_buf != NULL);
- assert(mt->num_samples <= 1 || mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+ assert(mt->surf.samples == 1 ||
+ mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
unreachable("Cannot get aux state for stencil");
} else {
{
bool aux_supported, clear_supported;
if (_mesa_is_format_color_format(mt->format)) {
- if (mt->num_samples > 1) {
+ if (mt->surf.samples > 1) {
aux_supported = clear_supported = true;
} else {
aux_supported = can_texture_with_ccs(brw, mt, view_format);
* enabled because otherwise the surface state will be programmed with
* the linear equivalent format anyway.
*/
- if (brw->gen == 9 && srgb_enabled && mt->num_samples <= 1 &&
+ if (brw->gen == 9 && srgb_enabled && mt->surf.samples == 1 &&
_mesa_get_srgb_format_linear(mt->format) != mt->format) {
/* Lossless compression is not supported for SRGB formats, it
* pixel data is stored. Fortunately this code path should never be
* reached for multisample buffers.
*/
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE || mt->num_samples <= 1);
+ assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_NONE ||
+ mt->surf.samples == 1);
intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
0, INTEL_REMAINING_LAYERS, false, false);
uint32_t tile_size = 4096;
uint32_t tile_width = 64;
uint32_t tile_height = 64;
- uint32_t row_size = 64 * stride;
+ uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
uint32_t tile_x = x / tile_width;
uint32_t tile_y = y / tile_height;
src->logical_width0,
src->logical_height0,
src->logical_depth0,
- src->num_samples,
+ src->surf.samples,
r8stencil_flags);
assert(mt->r8stencil_mt);
}
/* first_level */ 0,
/* last_level */ 0,
map->w, map->h, 1,
- /* samples */ 0,
+ /* samples */ 1,
MIPTREE_LAYOUT_TILING_NONE);
if (!map->linear_mt) {
* temporary buffer back out.
*/
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
- /* ISL uses a stencil pitch value that is expected by hardware whereas
- * traditional miptree uses half of that. Below the value gets supplied
- * to intel_offset_S8() which expects the legacy interpretation.
- */
const unsigned pitch = mt->surf.size > 0 ?
- mt->surf.row_pitch / 2 : mt->pitch;
+ mt->surf.row_pitch : mt->pitch;
uint8_t *untiled_s8_map = map->ptr;
uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt, GL_MAP_READ_BIT);
unsigned int image_x, image_y;
unsigned int slice)
{
if (map->mode & GL_MAP_WRITE_BIT) {
- /* ISL uses a stencil pitch value that is expected by hardware whereas
- * traditional miptree uses half of that. Below the value gets supplied
- * to intel_offset_S8() which expects the legacy interpretation.
- */
const unsigned pitch = mt->surf.size > 0 ?
- mt->surf.row_pitch / 2: mt->pitch;
+ mt->surf.row_pitch : mt->pitch;
unsigned int image_x, image_y;
uint8_t *untiled_s8_map = map->ptr;
uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT);
* temporary buffer back out.
*/
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
- /* ISL uses a stencil pitch value that is expected by hardware whereas
- * traditional miptree uses half of that. Below the value gets supplied
- * to intel_offset_S8() which expects the legacy interpretation.
- */
const unsigned s_pitch = s_mt->surf.size > 0 ?
- s_mt->surf.row_pitch / 2 : s_mt->pitch;
+ s_mt->surf.row_pitch : s_mt->pitch;
uint32_t *packed_map = map->ptr;
uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_READ_BIT);
uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_READ_BIT);
bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
if (map->mode & GL_MAP_WRITE_BIT) {
- /* ISL uses a stencil pitch value that is expected by hardware whereas
- * traditional miptree uses half of that. Below the value gets supplied
- * to intel_offset_S8() which expects the legacy interpretation.
- */
const unsigned s_pitch = s_mt->surf.size > 0 ?
- s_mt->surf.row_pitch / 2 : s_mt->pitch;
+ s_mt->surf.row_pitch : s_mt->pitch;
uint32_t *packed_map = map->ptr;
uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_WRITE_BIT);
uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_WRITE_BIT);
*/
!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
- (mt->tiling == I915_TILING_X ||
+ (mt->surf.tiling == ISL_TILING_X ||
/* Prior to Sandybridge, the blitter can't handle Y tiling */
- (brw->gen >= 6 && mt->tiling == I915_TILING_Y) ||
+ (brw->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) ||
/* Fast copy blit on skl+ supports all tiling formats. */
brw->gen >= 9) &&
can_blit_slice(mt, level, slice))
return true;
- if (mt->tiling != I915_TILING_NONE &&
+ if (mt->surf.tiling != ISL_TILING_LINEAR &&
mt->bo->size >= brw->max_gtt_map_object_size) {
assert(can_blit_slice(mt, level, slice));
return true;
{
struct intel_miptree_map *map;
- assert(mt->num_samples <= 1);
+ assert(mt->surf.samples == 1);
map = intel_miptree_attach_map(mt, level, slice, x, y, w, h, mode);
if (!map){
{
struct intel_miptree_map *map = mt->level[level].slice[slice].map;
- assert(mt->num_samples <= 1);
+ assert(mt->surf.samples == 1);
if (!map)
return;
}
enum isl_dim_layout
-get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
- GLenum target, enum miptree_array_layout array_layout)
+get_isl_dim_layout(const struct gen_device_info *devinfo,
+ enum isl_tiling tiling, GLenum target,
+ enum miptree_array_layout array_layout)
{
if (array_layout == GEN6_HIZ_STENCIL)
return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ;
switch (target) {
case GL_TEXTURE_1D:
case GL_TEXTURE_1D_ARRAY:
- return (devinfo->gen >= 9 && tiling == I915_TILING_NONE ?
+ return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
case GL_TEXTURE_2D:
enum isl_tiling
intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt)
{
- if (mt->format == MESA_FORMAT_S_UINT8) {
+ if (mt->format == MESA_FORMAT_S_UINT8)
return ISL_TILING_W;
- } else {
- switch (mt->tiling) {
- case I915_TILING_NONE:
- return ISL_TILING_LINEAR;
- case I915_TILING_X:
- return ISL_TILING_X;
- case I915_TILING_Y:
- return ISL_TILING_Y0;
- default:
- unreachable("Invalid tiling mode");
- }
- }
+ return mt->surf.tiling;
}
void
{
surf->dim = get_isl_surf_dim(mt->target);
surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo,
- mt->tiling, mt->target,
+ mt->surf.tiling, mt->target,
mt->array_layout);
-
- if (mt->num_samples > 1) {
- switch (mt->msaa_layout) {
- case INTEL_MSAA_LAYOUT_IMS:
- surf->msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
- break;
- case INTEL_MSAA_LAYOUT_UMS:
- case INTEL_MSAA_LAYOUT_CMS:
- surf->msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
- break;
- default:
- unreachable("Invalid MSAA layout");
- }
- } else {
- surf->msaa_layout = ISL_MSAA_LAYOUT_NONE;
- }
-
+ surf->msaa_layout = mt->surf.msaa_layout;
surf->tiling = intel_miptree_get_isl_tiling(mt);
-
- if (mt->format == MESA_FORMAT_S_UINT8) {
- /* The ISL definition of row_pitch matches the surface state pitch field
- * a bit better than intel_mipmap_tree. In particular, ISL incorporates
- * the factor of 2 for W-tiling in row_pitch.
- */
- surf->row_pitch = 2 * mt->pitch;
- } else {
- surf->row_pitch = mt->pitch;
- }
-
+ surf->row_pitch = mt->pitch;
surf->format = translate_tex_format(brw, mt->format, false);
if (brw->gen >= 9) {
}
surf->levels = mt->last_level - mt->first_level + 1;
- surf->samples = MAX2(mt->num_samples, 1);
+ surf->samples = mt->surf.samples;
surf->size = 0; /* TODO */
surf->alignment = 0; /* TODO */
projects / mesa.git / blobdiff