#include <GL/gl.h>
#include <GL/internal/dri_interface.h>
-#include <drm_fourcc.h>
+#include "drm-uapi/drm_fourcc.h"
#include "intel_batchbuffer.h"
#include "intel_image.h"
static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt);
-static bool
-intel_miptree_supports_mcs(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
-{
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
- /* MCS compression only applies to multisampled miptrees */
- if (mt->surf.samples <= 1)
- return false;
-
- /* Prior to Gen7, all MSAA surfaces used IMS layout. */
- if (devinfo->gen < 7)
- return false;
-
- /* See isl_surf_get_mcs_surf for details. */
- if (mt->surf.samples == 16 && mt->surf.logical_level0_px.width > 8192)
- return false;
-
- /* In Gen7, IMS layout is only used for depth and stencil buffers. */
- switch (_mesa_get_format_base_format(mt->format)) {
- case GL_DEPTH_COMPONENT:
- case GL_STENCIL_INDEX:
- case GL_DEPTH_STENCIL:
- return false;
- default:
- /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
- *
- * This field must be set to 0 for all SINT MSRTs when all RT channels
- * are not written
- *
- * In practice this means that we have to disable MCS for all signed
- * integer MSAA buffers. The alternative, to disable MCS only when one
- * of the render target channels is disabled, is impractical because it
- * would require converting between CMS and UMS MSAA layouts on the fly,
- * which is expensive.
- */
- if (devinfo->gen == 7 && _mesa_get_format_datatype(mt->format) == GL_INT) {
- return false;
- } else {
- return true;
- }
- }
-}
-
-static bool
-intel_tiling_supports_ccs(const struct brw_context *brw,
- enum isl_tiling tiling)
-{
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
- /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
- * Target(s)", beneath the "Fast Color Clear" bullet (p326):
- *
- * - Support is limited to tiled render targets.
- *
- * Gen9 changes the restriction to Y-tile only.
- */
- if (devinfo->gen >= 9)
- return tiling == ISL_TILING_Y0;
- else if (devinfo->gen >= 7)
- return tiling != ISL_TILING_LINEAR;
- else
- return false;
-}
-
-/**
- * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
- * can be used. This doesn't (and should not) inspect any of the properties of
- * the miptree's BO.
- *
- * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
- * beneath the "Fast Color Clear" bullet (p326):
- *
- * - Support is for non-mip-mapped and non-array surface types only.
- *
- * And then later, on p327:
- *
- * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
- * 64bpp, and 128bpp.
- *
- * From the Skylake documentation, it is made clear that X-tiling is no longer
- * supported:
- *
- * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
- * non-MSRTs only.
- */
-static bool
-intel_miptree_supports_ccs(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
-{
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
- /* MCS support does not exist prior to Gen7 */
- if (devinfo->gen < 7)
- return false;
-
- /* This function applies only to non-multisampled render targets. */
- if (mt->surf.samples > 1)
- return false;
-
- /* MCS is only supported for color buffers */
- if (!_mesa_is_format_color_format(mt->format))
- return false;
-
- if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
- return false;
-
- const bool mip_mapped = mt->first_level != 0 || mt->last_level != 0;
- const bool arrayed = mt->surf.logical_level0_px.array_len > 1 ||
- mt->surf.logical_level0_px.depth > 1;
-
- if (arrayed) {
- /* Multisample surfaces with the CMS layout are not layered surfaces,
- * yet still have physical_depth0 > 1. Assert that we don't
- * accidentally reject a multisampled surface here. We should have
- * rejected it earlier by explicitly checking the sample count.
- */
- assert(mt->surf.samples == 1);
- }
-
- /* Handle the hardware restrictions...
- *
- * All GENs have the following restriction: "MCS buffer for non-MSRT is
- * supported only for RT formats 32bpp, 64bpp, and 128bpp."
- *
- * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
- * Non-MultiSampler Render Target Restrictions) Support is for
- * non-mip-mapped and non-array surface types only.
- *
- * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
- * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
- * surfaces are supported with MCS buffer layout with these alignments in
- * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
- *
- * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
- * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
- * surfaces are supported with MCS buffer layout with these alignments in
- * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
- */
- if (devinfo->gen < 8 && (mip_mapped || arrayed))
- return false;
-
- /* The PRM doesn't say this explicitly, but fast-clears don't appear to
- * work for 3D textures until gen9 where the layout of 3D textures changes
- * to match 2D array textures.
- */
- if (devinfo->gen <= 8 && mt->surf.dim != ISL_SURF_DIM_2D)
- return false;
-
- /* There's no point in using an MCS buffer if the surface isn't in a
- * renderable format.
- */
- if (!brw->mesa_format_supports_render[mt->format])
- return false;
-
- return true;
-}
-
-static bool
-intel_tiling_supports_hiz(const struct brw_context *brw,
- enum isl_tiling tiling)
-{
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
- if (devinfo->gen < 6)
- return false;
-
- return tiling == ISL_TILING_Y0;
-}
-
-static bool
-intel_miptree_supports_hiz(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
-{
- if (!brw->has_hiz)
- return false;
-
- switch (mt->format) {
- case MESA_FORMAT_Z_FLOAT32:
- case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
- case MESA_FORMAT_Z24_UNORM_X8_UINT:
- case MESA_FORMAT_Z24_UNORM_S8_UINT:
- case MESA_FORMAT_Z_UNORM16:
- return true;
- default:
- return false;
- }
-}
-
/**
* Return true if the format that will be used to access the miptree is
* CCS_E-compatible with the miptree's linear/non-sRGB format.
return isl_formats_are_ccs_e_compatible(devinfo, isl_format, access_format);
}
+/* Determine if CCS_E is supported for a given platform and mesa format. */
static bool
-intel_miptree_supports_ccs_e(struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
+format_supports_ccs_e(const struct brw_context *brw, mesa_format format)
{
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
- if (devinfo->gen < 9)
- return false;
-
/* For now compression is only enabled for integer formats even though
* there exist supported floating point formats also. This is a heuristic
* decision based on current public benchmarks. In none of the cases these
* Hence these are left to to be enabled in the future when they are known
* to improve things.
*/
- if (_mesa_get_format_datatype(mt->format) == GL_FLOAT)
- return false;
-
- if (!intel_miptree_supports_ccs(brw, mt))
+ if (_mesa_get_format_datatype(format) == GL_FLOAT)
return false;
/* Many window system buffers are sRGB even if they are never rendered as
* sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
* surface is used as sRGB, we fall back to CCS_D.
*/
- mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+ mesa_format linear_format = _mesa_get_srgb_format_linear(format);
enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
return isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format);
}
if (devinfo->must_use_separate_stencil)
return true;
- return brw->has_separate_stencil &&
- intel_miptree_supports_hiz(brw, mt);
+ return brw->has_separate_stencil && brw->has_hiz;
}
/**
{
assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
- if (intel_miptree_supports_mcs(brw, mt)) {
- assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
- mt->aux_usage = ISL_AUX_USAGE_MCS;
- } else if (intel_tiling_supports_ccs(brw, mt->surf.tiling) &&
- intel_miptree_supports_ccs(brw, mt)) {
- if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
- intel_miptree_supports_ccs_e(brw, mt)) {
+ if (_mesa_is_format_color_format(mt->format)) {
+ if (mt->surf.samples > 1) {
+ mt->aux_usage = ISL_AUX_USAGE_MCS;
+ } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ format_supports_ccs_e(brw, mt->format)) {
mt->aux_usage = ISL_AUX_USAGE_CCS_E;
- } else {
+ } else if (brw->mesa_format_supports_render[mt->format]) {
mt->aux_usage = ISL_AUX_USAGE_CCS_D;
}
- } else if (intel_tiling_supports_hiz(brw, mt->surf.tiling) &&
- intel_miptree_supports_hiz(brw, mt)) {
+ } else if (isl_surf_usage_is_depth(mt->surf.usage) && brw->has_hiz) {
mt->aux_usage = ISL_AUX_USAGE_HIZ;
}
}
static bool
-need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
+need_to_retile_as_linear(struct brw_context *brw, unsigned blt_pitch,
enum isl_tiling tiling, unsigned samples)
{
if (samples > 1)
if (tiling == ISL_TILING_LINEAR)
return false;
- /* If the width is much smaller than a tile, don't bother tiling. */
- if (row_pitch < 64)
- return true;
-
- if (ALIGN(row_pitch, 512) >= 32768) {
- perf_debug("row pitch %u too large to blit, falling back to untiled",
- row_pitch);
+ if (blt_pitch >= 32768) {
+ perf_debug("blt pitch %u too large to blit, falling back to untiled",
+ blt_pitch);
return true;
}
unsigned width0, unsigned height0, unsigned depth0,
unsigned num_samples, isl_tiling_flags_t tiling_flags,
isl_surf_usage_flags_t isl_usage_flags, uint32_t alloc_flags,
- unsigned row_pitch, struct brw_bo *bo)
+ unsigned row_pitch_B, struct brw_bo *bo)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
.levels = last_level - first_level + 1,
.array_len = target == GL_TEXTURE_3D ? 1 : depth0,
.samples = num_samples,
- .row_pitch = row_pitch,
+ .row_pitch_B = row_pitch_B,
.usage = isl_usage_flags,
.tiling_flags = tiling_flags,
};
bool is_depth_stencil =
mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
if (!is_depth_stencil) {
- if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
+ if (need_to_retile_as_linear(brw, intel_miptree_blt_pitch(mt),
mt->surf.tiling, mt->surf.samples)) {
init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
- } else if (need_to_retile_as_x(brw, mt->surf.size, mt->surf.tiling)) {
+ } else if (need_to_retile_as_x(brw, mt->surf.size_B, mt->surf.tiling)) {
init_info.tiling_flags = 1u << ISL_TILING_X;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
* See isl_apply_surface_padding().
*/
if (mt->surf.tiling != ISL_TILING_LINEAR)
- assert(mt->surf.size % mt->surf.row_pitch == 0);
+ assert(mt->surf.size_B % mt->surf.row_pitch_B == 0);
if (!bo) {
mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
- mt->surf.size,
+ mt->surf.size_B,
BRW_MEMZONE_OTHER,
isl_tiling_to_i915_tiling(
mt->surf.tiling),
- mt->surf.row_pitch, alloc_flags);
+ mt->surf.row_pitch_B, alloc_flags);
if (!mt->bo)
goto fail;
} else {
return NULL;
}
-static bool
-make_separate_stencil_surface(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+/* Return the usual surface usage flags for the given format. */
+static isl_surf_usage_flags_t
+mt_surf_usage(mesa_format format)
{
- mt->stencil_mt = make_surface(brw, mt->target, MESA_FORMAT_S_UINT8,
- 0, mt->surf.levels - 1,
- mt->surf.logical_level0_px.width,
- mt->surf.logical_level0_px.height,
- mt->surf.dim == ISL_SURF_DIM_3D ?
- mt->surf.logical_level0_px.depth :
- mt->surf.logical_level0_px.array_len,
- mt->surf.samples, ISL_TILING_W_BIT,
- ISL_SURF_USAGE_STENCIL_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY, 0, NULL);
-
- if (!mt->stencil_mt)
- return false;
-
- mt->stencil_mt->r8stencil_needs_update = true;
-
- return true;
+ switch(_mesa_get_format_base_format(format)) {
+ case GL_DEPTH_COMPONENT:
+ return ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ case GL_DEPTH_STENCIL:
+ return ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT;
+ case GL_STENCIL_INDEX:
+ return ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ default:
+ return ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ }
}
static struct intel_mipmap_tree *
enum intel_miptree_create_flags flags)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const uint32_t alloc_flags =
+ (flags & MIPTREE_CREATE_BUSY || num_samples > 1) ? BO_ALLOC_BUSY : 0;
+ isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
- if (format == MESA_FORMAT_S_UINT8)
- return make_surface(brw, target, format, first_level, last_level,
- width0, height0, depth0, num_samples,
- ISL_TILING_W_BIT,
- ISL_SURF_USAGE_STENCIL_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY,
- 0,
- NULL);
+ /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
+ if (devinfo->gen < 6 && _mesa_is_format_color_format(format))
+ tiling_flags &= ~ISL_TILING_Y0_BIT;
- const GLenum base_format = _mesa_get_format_base_format(format);
- if ((base_format == GL_DEPTH_COMPONENT ||
- base_format == GL_DEPTH_STENCIL) &&
- !(flags & MIPTREE_CREATE_LINEAR)) {
+ mesa_format mt_fmt = format;
+ if (!_mesa_is_format_color_format(format) && devinfo->gen >= 6) {
/* Fix up the Z miptree format for how we're splitting out separate
- * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
+ * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
*/
- const mesa_format depth_only_format =
- intel_depth_format_for_depthstencil_format(format);
- struct intel_mipmap_tree *mt = make_surface(
- brw, target, devinfo->gen >= 6 ? depth_only_format : format,
- first_level, last_level,
- width0, height0, depth0, num_samples, ISL_TILING_Y0_BIT,
- ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY, 0, NULL);
-
- if (needs_separate_stencil(brw, mt, format) &&
- !make_separate_stencil_surface(brw, mt)) {
- intel_miptree_release(&mt);
- return NULL;
- }
-
- if (!(flags & MIPTREE_CREATE_NO_AUX))
- intel_miptree_choose_aux_usage(brw, mt);
-
- return mt;
+ mt_fmt = intel_depth_format_for_depthstencil_format(format);
}
- mesa_format tex_format = format;
- mesa_format etc_format = MESA_FORMAT_NONE;
- uint32_t alloc_flags = 0;
-
- format = intel_lower_compressed_format(brw, format);
-
- etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
-
- if (flags & MIPTREE_CREATE_BUSY)
- alloc_flags |= BO_ALLOC_BUSY;
+ struct intel_mipmap_tree *mt =
+ make_surface(brw, target, mt_fmt, first_level, last_level,
+ width0, height0, depth0, num_samples,
+ tiling_flags, mt_surf_usage(mt_fmt),
+ alloc_flags, 0, NULL);
- isl_tiling_flags_t tiling_flags = (flags & MIPTREE_CREATE_LINEAR) ?
- ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
+ if (mt == NULL)
+ return NULL;
- /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
- if (devinfo->gen < 6)
- tiling_flags &= ~ISL_TILING_Y0_BIT;
+ if (intel_miptree_needs_fake_etc(brw, mt)) {
+ mesa_format decomp_format = intel_lower_compressed_format(brw, format);
+ mt->shadow_mt = make_surface(brw, target, decomp_format, first_level,
+ last_level, width0, height0, depth0,
+ num_samples, tiling_flags,
+ mt_surf_usage(decomp_format),
+ alloc_flags, 0, NULL);
- struct intel_mipmap_tree *mt = make_surface(
- brw, target, format,
- first_level, last_level,
- width0, height0, depth0,
- num_samples, tiling_flags,
- ISL_SURF_USAGE_RENDER_TARGET_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
- alloc_flags, 0, NULL);
- if (!mt)
- return NULL;
+ if (mt->shadow_mt == NULL) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
- mt->etc_format = etc_format;
+ if (needs_separate_stencil(brw, mt, format)) {
+ mt->stencil_mt =
+ make_surface(brw, target, MESA_FORMAT_S_UINT8, first_level, last_level,
+ width0, height0, depth0, num_samples,
+ ISL_TILING_W_BIT, mt_surf_usage(MESA_FORMAT_S_UINT8),
+ alloc_flags, 0, NULL);
+ if (mt->stencil_mt == NULL) {
+ intel_miptree_release(&mt);
+ return NULL;
+ }
+ }
if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
*/
if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
!intel_miptree_alloc_aux(brw, mt)) {
- intel_miptree_release(&mt);
- return NULL;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
}
return mt;
if ((base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL)) {
- const mesa_format depth_only_format =
+ const mesa_format mt_fmt = (devinfo->gen < 6) ? format :
intel_depth_format_for_depthstencil_format(format);
- mt = make_surface(brw, target,
- devinfo->gen >= 6 ? depth_only_format : format,
+ mt = make_surface(brw, target, mt_fmt,
0, 0, width, height, depth, 1, ISL_TILING_Y0_BIT,
- ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
+ mt_surf_usage(mt_fmt),
0, pitch, bo);
if (!mt)
return NULL;
mt = make_surface(brw, target, MESA_FORMAT_S_UINT8,
0, 0, width, height, depth, 1,
ISL_TILING_W_BIT,
- ISL_SURF_USAGE_STENCIL_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
+ mt_surf_usage(MESA_FORMAT_S_UINT8),
0, pitch, bo);
if (!mt)
return NULL;
- assert(bo->size >= mt->surf.size);
+ assert(bo->size >= mt->surf.size_B);
brw_bo_reference(bo);
return mt;
*/
assert(pitch >= 0);
- /* The BO already has a tiling format and we shouldn't confuse the lower
- * layers by making it try to find a tiling format again.
- */
- assert((flags & MIPTREE_CREATE_LINEAR) == 0);
-
mt = make_surface(brw, target, format,
0, 0, width, height, depth, 1,
1lu << tiling,
- ISL_SURF_USAGE_RENDER_TARGET_BIT |
- ISL_SURF_USAGE_TEXTURE_BIT,
+ mt_surf_usage(format),
0, pitch, bo);
if (!mt)
return NULL;
*/
if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
!intel_miptree_alloc_aux(brw, mt)) {
- intel_miptree_release(&mt);
- return NULL;
+ mt->aux_usage = ISL_AUX_USAGE_NONE;
+ mt->supports_fast_clear = false;
}
}
return false;
assert(image->aux_offset < image->bo->size);
- assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+ assert(temp_ccs_surf.size_B <= image->bo->size - image->aux_offset);
mt->aux_buf = calloc(sizeof(*mt->aux_buf), 1);
if (mt->aux_buf == NULL)
brw_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
- intel_miptree_release(&(*mt)->r8stencil_mt);
+ intel_miptree_release(&(*mt)->shadow_mt);
intel_miptree_aux_buffer_free((*mt)->aux_buf);
free_aux_state_map((*mt)->aux_state);
mt_format = MESA_FORMAT_Z24_UNORM_S8_UINT;
if (mt->format == MESA_FORMAT_Z_FLOAT32 && mt->stencil_mt)
mt_format = MESA_FORMAT_Z32_FLOAT_S8X24_UINT;
- if (mt->etc_format != MESA_FORMAT_NONE)
- mt_format = mt->etc_format;
if (_mesa_get_srgb_format_linear(image->TexFormat) !=
_mesa_get_srgb_format_linear(mt_format))
uint32_t x, uint32_t y)
{
int cpp = mt->cpp;
- uint32_t pitch = mt->surf.row_pitch;
+ uint32_t pitch = mt->surf.row_pitch_B;
switch (mt->surf.tiling) {
default:
DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
_mesa_get_format_name(src_mt->format),
- src_mt, src_x, src_y, src_mt->surf.row_pitch,
+ src_mt, src_x, src_y, src_mt->surf.row_pitch_B,
_mesa_get_format_name(dst_mt->format),
- dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch,
+ dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch_B,
width, height);
if (!intel_miptree_blit(brw,
if (!buf)
return false;
- uint64_t size = aux_surf->size;
+ uint64_t size = aux_surf->size_B;
const bool has_indirect_clear = brw->isl_dev.ss.clear_color_state_size > 0;
if (has_indirect_clear) {
*/
buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "aux-miptree", size,
BRW_MEMZONE_OTHER, I915_TILING_Y,
- aux_surf->row_pitch, alloc_flags);
+ aux_surf->row_pitch_B, alloc_flags);
if (!buf->bo) {
free(buf);
return NULL;
/* Memset the aux_surf portion of the BO. */
if (wants_memset)
- memset(map, memset_value, aux_surf->size);
+ memset(map, memset_value, aux_surf->size_B);
/* Zero the indirect clear color to match ::fast_clear_color. */
if (has_indirect_clear) {
const struct gen_device_info *devinfo = &brw->screen->devinfo;
assert(mt->aux_buf);
- assert(mt->surf.size > 0);
+ assert(mt->surf.size_B > 0);
if (devinfo->gen >= 8 || devinfo->is_haswell) {
uint32_t width = minify(mt->surf.phys_level0_sa.width, level);
enum isl_aux_state initial_state;
uint8_t memset_value;
struct isl_surf aux_surf;
- MAYBE_UNUSED bool aux_surf_ok;
+ MAYBE_UNUSED bool aux_surf_ok = false;
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
- aux_surf.size = 0;
+ aux_surf.size_B = 0;
aux_surf_ok = true;
break;
case ISL_AUX_USAGE_HIZ:
initial_state = ISL_AUX_STATE_AUX_INVALID;
+ memset_value = 0;
aux_surf_ok = isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &aux_surf);
break;
case ISL_AUX_USAGE_MCS:
}
/* We should have a valid aux_surf. */
- assert(aux_surf_ok);
+ if (!aux_surf_ok)
+ return false;
/* No work is needed for a zero-sized auxiliary buffer. */
- if (aux_surf.size == 0)
+ if (aux_surf.size_B == 0)
return true;
/* Create the aux_state for the auxiliary buffer. */
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_usage aux_usage)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
- /* Nothing to do */
+ if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7) {
+ mt->shadow_needs_update = true;
+ } else if (intel_miptree_has_etc_shadow(brw, mt)) {
+ mt->shadow_needs_update = true;
+ }
break;
case ISL_AUX_USAGE_MCS:
enum isl_aux_usage
intel_miptree_texture_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- enum isl_format view_format)
+ enum isl_format view_format,
+ enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
{
+ assert(brw->screen->devinfo.gen == 9 || astc5x5_wa_bits == 0);
+
+ /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
+ * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
+ * details.
+ */
+ if ((astc5x5_wa_bits & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
+ mt->aux_usage != ISL_AUX_USAGE_MCS)
+ return ISL_AUX_USAGE_NONE;
+
switch (mt->aux_usage) {
case ISL_AUX_USAGE_HIZ:
if (intel_miptree_sample_with_hiz(brw, mt))
struct intel_mipmap_tree *mt,
enum isl_format view_format,
uint32_t start_level, uint32_t num_levels,
- uint32_t start_layer, uint32_t num_layers)
+ uint32_t start_layer, uint32_t num_layers,
+ enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
{
enum isl_aux_usage aux_usage =
- intel_miptree_texture_aux_usage(brw, mt, view_format);
+ intel_miptree_texture_aux_usage(brw, mt, view_format, astc5x5_wa_bits);
+
bool clear_supported = aux_usage != ISL_AUX_USAGE_NONE;
/* Clear color is specified as ints or floats and the conversion is done by
{
if (depth_written) {
intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
- mt->aux_buf != NULL);
+ mt->aux_usage);
}
}
assert(devinfo->gen >= 7);
struct intel_mipmap_tree *src =
mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt;
- if (!src || devinfo->gen >= 8 || !src->r8stencil_needs_update)
+ if (!src || devinfo->gen >= 8)
return;
- assert(src->surf.size > 0);
+ assert(src->surf.size_B > 0);
- if (!mt->r8stencil_mt) {
+ if (!mt->shadow_mt) {
assert(devinfo->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
- mt->r8stencil_mt = make_surface(
+ mt->shadow_mt = make_surface(
brw,
src->target,
MESA_FORMAT_R_UINT8,
ISL_TILING_Y0_BIT,
ISL_SURF_USAGE_TEXTURE_BIT,
BO_ALLOC_BUSY, 0, NULL);
- assert(mt->r8stencil_mt);
+ assert(mt->shadow_mt);
}
- struct intel_mipmap_tree *dst = mt->r8stencil_mt;
+ if (src->shadow_needs_update == false)
+ return;
+
+ struct intel_mipmap_tree *dst = mt->shadow_mt;
for (int level = src->first_level; level <= src->last_level; level++) {
const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
}
brw_cache_flush_for_read(brw, dst->bo);
- src->r8stencil_needs_update = false;
+ src->shadow_needs_update = false;
}
static void *
}
static void
-intel_miptree_unmap_gtt(struct brw_context *brw,
+intel_miptree_unmap_map(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
}
static void
-intel_miptree_map_gtt(struct brw_context *brw,
+intel_miptree_map_map(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
x += image_x;
y += image_y;
- map->stride = mt->surf.row_pitch;
+ map->stride = mt->surf.row_pitch_B;
map->ptr = base + y * map->stride + x * mt->cpp;
}
mt, _mesa_get_format_name(mt->format),
x, y, map->ptr, map->stride);
- map->unmap = intel_miptree_unmap_gtt;
+ map->unmap = intel_miptree_unmap_map;
}
static void
intel_miptree_release(&map->linear_mt);
}
+/* Compute extent parameters for use with tiled_memcpy functions.
+ * xs are in units of bytes and ys are in units of strides.
+ */
+static inline void
+tile_extents(struct intel_mipmap_tree *mt, struct intel_miptree_map *map,
+ unsigned int level, unsigned int slice, unsigned int *x1_B,
+ unsigned int *x2_B, unsigned int *y1_el, unsigned int *y2_el)
+{
+ unsigned int block_width, block_height;
+ unsigned int x0_el, y0_el;
+
+ _mesa_get_format_block_size(mt->format, &block_width, &block_height);
+
+ assert(map->x % block_width == 0);
+ assert(map->y % block_height == 0);
+
+ intel_miptree_get_image_offset(mt, level, slice, &x0_el, &y0_el);
+ *x1_B = (map->x / block_width + x0_el) * mt->cpp;
+ *y1_el = map->y / block_height + y0_el;
+ *x2_B = (DIV_ROUND_UP(map->x + map->w, block_width) + x0_el) * mt->cpp;
+ *y2_el = DIV_ROUND_UP(map->y + map->h, block_height) + y0_el;
+}
+
+static void
+intel_miptree_unmap_tiled_memcpy(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
+{
+ if (map->mode & GL_MAP_WRITE_BIT) {
+ unsigned int x1, x2, y1, y2;
+ tile_extents(mt, map, level, slice, &x1, &x2, &y1, &y2);
+
+ char *dst = intel_miptree_map_raw(brw, mt, map->mode | MAP_RAW);
+ dst += mt->offset;
+
+ isl_memcpy_linear_to_tiled(
+ x1, x2, y1, y2, dst, map->ptr, mt->surf.row_pitch_B, map->stride,
+ brw->has_swizzling, mt->surf.tiling, ISL_MEMCPY);
+
+ intel_miptree_unmap_raw(mt);
+ }
+ _mesa_align_free(map->buffer);
+ map->buffer = map->ptr = NULL;
+}
+
+/**
+ * Determine which copy function to use for the given format combination
+ *
+ * The only two possible copy functions which are ever returned are a
+ * direct memcpy and a RGBA <-> BGRA copy function. Since RGBA -> BGRA and
+ * BGRA -> RGBA are exactly the same operation (and memcpy is obviously
+ * symmetric), it doesn't matter whether the copy is from the tiled image
+ * to the untiled or vice versa. The copy function required is the same in
+ * either case so this function can be used.
+ *
+ * \param[in] tiledFormat The format of the tiled image
+ * \param[in] format The GL format of the client data
+ * \param[in] type The GL type of the client data
+ * \param[out] mem_copy Will be set to one of either the standard
+ * library's memcpy or a different copy function
+ * that performs an RGBA to BGRA conversion
+ * \param[out] cpp Number of bytes per channel
+ *
+ * \return true if the format and type combination are valid
+ */
+MAYBE_UNUSED isl_memcpy_type
+intel_miptree_get_memcpy_type(mesa_format tiledFormat, GLenum format, GLenum type,
+ uint32_t *cpp)
+{
+ if (type == GL_UNSIGNED_INT_8_8_8_8_REV &&
+ !(format == GL_RGBA || format == GL_BGRA))
+ return ISL_MEMCPY_INVALID; /* Invalid type/format combination */
+
+ if ((tiledFormat == MESA_FORMAT_L_UNORM8 && format == GL_LUMINANCE) ||
+ (tiledFormat == MESA_FORMAT_A_UNORM8 && format == GL_ALPHA)) {
+ *cpp = 1;
+ return ISL_MEMCPY;
+ } else if ((tiledFormat == MESA_FORMAT_B8G8R8A8_UNORM) ||
+ (tiledFormat == MESA_FORMAT_B8G8R8X8_UNORM) ||
+ (tiledFormat == MESA_FORMAT_B8G8R8A8_SRGB) ||
+ (tiledFormat == MESA_FORMAT_B8G8R8X8_SRGB)) {
+ *cpp = 4;
+ if (format == GL_BGRA) {
+ return ISL_MEMCPY;
+ } else if (format == GL_RGBA) {
+ return ISL_MEMCPY_BGRA8;
+ }
+ } else if ((tiledFormat == MESA_FORMAT_R8G8B8A8_UNORM) ||
+ (tiledFormat == MESA_FORMAT_R8G8B8X8_UNORM) ||
+ (tiledFormat == MESA_FORMAT_R8G8B8A8_SRGB) ||
+ (tiledFormat == MESA_FORMAT_R8G8B8X8_SRGB)) {
+ *cpp = 4;
+ if (format == GL_BGRA) {
+ /* Copying from RGBA to BGRA is the same as BGRA to RGBA so we can
+ * use the same function.
+ */
+ return ISL_MEMCPY_BGRA8;
+ } else if (format == GL_RGBA) {
+ return ISL_MEMCPY;
+ }
+ }
+
+ return ISL_MEMCPY_INVALID;
+}
+
+static void
+intel_miptree_map_tiled_memcpy(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level, unsigned int slice)
+{
+ intel_miptree_access_raw(brw, mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
+
+ unsigned int x1, x2, y1, y2;
+ tile_extents(mt, map, level, slice, &x1, &x2, &y1, &y2);
+ map->stride = ALIGN(_mesa_format_row_stride(mt->format, map->w), 16);
+
+ /* The tiling and detiling functions require that the linear buffer
+ * has proper 16-byte alignment (that is, its `x0` is 16-byte
+ * aligned). Here we over-allocate the linear buffer by enough
+ * bytes to get the proper alignment.
+ */
+ map->buffer = _mesa_align_malloc(map->stride * (y2 - y1) + (x1 & 0xf), 16);
+ map->ptr = (char *)map->buffer + (x1 & 0xf);
+ assert(map->buffer);
+
+ if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
+ char *src = intel_miptree_map_raw(brw, mt, map->mode | MAP_RAW);
+ src += mt->offset;
+
+ const isl_memcpy_type copy_type =
+#if defined(USE_SSE41)
+ cpu_has_sse4_1 ? ISL_MEMCPY_STREAMING_LOAD :
+#endif
+ ISL_MEMCPY;
+
+ isl_memcpy_tiled_to_linear(
+ x1, x2, y1, y2, map->ptr, src, map->stride,
+ mt->surf.row_pitch_B, brw->has_swizzling, mt->surf.tiling,
+ copy_type);
+
+ intel_miptree_unmap_raw(mt);
+ }
+
+ map->unmap = intel_miptree_unmap_tiled_memcpy;
+}
+
static void
intel_miptree_map_blit(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
- map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
- /* first_level */ 0,
- /* last_level */ 0,
- map->w, map->h, 1,
- /* samples */ 1,
- MIPTREE_CREATE_LINEAR);
+ map->linear_mt = make_surface(brw, GL_TEXTURE_2D, mt->format,
+ 0, 0, map->w, map->h, 1, 1,
+ ISL_TILING_LINEAR_BIT,
+ ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ 0, 0, NULL);
if (!map->linear_mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
goto fail;
}
- map->stride = map->linear_mt->surf.row_pitch;
+ map->stride = map->linear_mt->surf.row_pitch_B;
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
src += mt->offset;
- src += image_y * mt->surf.row_pitch;
+ src += image_y * mt->surf.row_pitch_B;
src += image_x * mt->cpp;
/* Due to the pixel offsets for the particular image being mapped, our
* divisible by 16, then the amount by which it's misaligned will remain
* consistent from row to row.
*/
- assert((mt->surf.row_pitch % 16) == 0);
+ assert((mt->surf.row_pitch_B % 16) == 0);
const int misalignment = ((uintptr_t) src) & 15;
/* Create an untiled temporary buffer for the mapping. */
for (uint32_t y = 0; y < map->h; y++) {
void *dst_ptr = map->ptr + y * map->stride;
- void *src_ptr = src + y * mt->surf.row_pitch;
+ void *src_ptr = src + y * mt->surf.row_pitch_B;
_mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes);
}
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch,
+ ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch_B,
image_x + x + map->x,
image_y + y + map->y,
brw->has_swizzling);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch,
+ ptrdiff_t offset = intel_offset_S8(mt->surf.row_pitch_B,
x + image_x + map->x,
y + image_y + map->y,
brw->has_swizzling);
map->unmap = intel_miptree_unmap_s8;
}
-static void
-intel_miptree_unmap_etc(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
-{
- uint32_t image_x;
- uint32_t image_y;
- intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
-
- image_x += map->x;
- image_y += map->y;
-
- uint8_t *dst = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT)
- + image_y * mt->surf.row_pitch
- + image_x * mt->cpp;
-
- if (mt->etc_format == MESA_FORMAT_ETC1_RGB8)
- _mesa_etc1_unpack_rgba8888(dst, mt->surf.row_pitch,
- map->ptr, map->stride,
- map->w, map->h);
- else
- _mesa_unpack_etc2_format(dst, mt->surf.row_pitch,
- map->ptr, map->stride,
- map->w, map->h, mt->etc_format);
-
- intel_miptree_unmap_raw(mt);
- free(map->buffer);
-}
-
-static void
-intel_miptree_map_etc(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
-{
- assert(mt->etc_format != MESA_FORMAT_NONE);
- if (mt->etc_format == MESA_FORMAT_ETC1_RGB8) {
- assert(mt->format == MESA_FORMAT_R8G8B8X8_UNORM);
- }
-
- assert(map->mode & GL_MAP_WRITE_BIT);
- assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
-
- intel_miptree_access_raw(brw, mt, level, slice, true);
-
- map->stride = _mesa_format_row_stride(mt->etc_format, map->w);
- map->buffer = malloc(_mesa_format_image_size(mt->etc_format,
- map->w, map->h, 1));
- map->ptr = map->buffer;
- map->unmap = intel_miptree_unmap_etc;
-}
-
/**
* Mapping functions for packed depth/stencil miptrees backed by real separate
* miptrees for depth and stencil.
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
- ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch_B,
x + s_image_x + map->x,
y + s_image_y + map->y,
brw->has_swizzling);
ptrdiff_t z_offset = ((y + z_image_y + map->y) *
- (z_mt->surf.row_pitch / 4) +
+ (z_mt->surf.row_pitch_B / 4) +
(x + z_image_x + map->x));
if (map_z32f_x24s8) {
if (!map->buffer)
return;
- intel_miptree_access_raw(brw, mt, level, slice,
+ intel_miptree_access_raw(brw, z_mt, level, slice,
+ map->mode & GL_MAP_WRITE_BIT);
+ intel_miptree_access_raw(brw, s_mt, level, slice,
map->mode & GL_MAP_WRITE_BIT);
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
int map_x = map->x + x, map_y = map->y + y;
- ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch,
+ ptrdiff_t s_offset = intel_offset_S8(s_mt->surf.row_pitch_B,
map_x + s_image_x,
map_y + s_image_y,
brw->has_swizzling);
ptrdiff_t z_offset = ((map_y + z_image_y) *
- (z_mt->surf.row_pitch / 4) +
+ (z_mt->surf.row_pitch_B / 4) +
(map_x + z_image_x));
uint8_t s = s_map[s_offset];
uint32_t z = z_map[z_offset];
static bool
can_blit_slice(struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int slice)
+ const struct intel_miptree_map *map)
{
/* See intel_miptree_blit() for details on the 32k pitch limit. */
- if (mt->surf.row_pitch >= 32768)
- return false;
-
- return true;
+ const unsigned src_blt_pitch = intel_miptree_blt_pitch(mt);
+ const unsigned dst_blt_pitch = ALIGN(map->w * mt->cpp, 64);
+ return src_blt_pitch < 32768 && dst_blt_pitch < 32768;
}
static bool
use_intel_mipree_map_blit(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- GLbitfield mode,
- unsigned int level,
- unsigned int slice)
+ const struct intel_miptree_map *map)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
/* It's probably not worth swapping to the blit ring because of
* all the overhead involved.
*/
- !(mode & GL_MAP_WRITE_BIT) &&
+ !(map->mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
(mt->surf.tiling == ISL_TILING_X ||
/* Prior to Sandybridge, the blitter can't handle Y tiling */
(devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) ||
/* Fast copy blit on skl+ supports all tiling formats. */
devinfo->gen >= 9) &&
- can_blit_slice(mt, level, slice))
+ can_blit_slice(mt, map))
return true;
if (mt->surf.tiling != ISL_TILING_LINEAR &&
mt->bo->size >= brw->max_gtt_map_object_size) {
- assert(can_blit_slice(mt, level, slice));
+ assert(can_blit_slice(mt, map));
return true;
}
void **out_ptr,
ptrdiff_t *out_stride)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct intel_miptree_map *map;
assert(mt->surf.samples == 1);
if (mt->format == MESA_FORMAT_S_UINT8) {
intel_miptree_map_s8(brw, mt, map, level, slice);
- } else if (mt->etc_format != MESA_FORMAT_NONE &&
- !(mode & BRW_MAP_DIRECT_BIT)) {
- intel_miptree_map_etc(brw, mt, map, level, slice);
} else if (mt->stencil_mt && !(mode & BRW_MAP_DIRECT_BIT)) {
intel_miptree_map_depthstencil(brw, mt, map, level, slice);
- } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
+ } else if (use_intel_mipree_map_blit(brw, mt, map)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
+ } else if (mt->surf.tiling != ISL_TILING_LINEAR && devinfo->gen > 4) {
+ intel_miptree_map_tiled_memcpy(brw, mt, map, level, slice);
#if defined(USE_SSE41)
} else if (!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed && cpu_has_sse4_1 &&
- (mt->surf.row_pitch % 16 == 0)) {
+ (mt->surf.row_pitch_B % 16 == 0)) {
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {
- intel_miptree_map_gtt(brw, mt, map, level, slice);
+ if (mt->surf.tiling != ISL_TILING_LINEAR)
+ perf_debug("intel_miptree_map: mapping via gtt");
+ intel_miptree_map_map(brw, mt, map, level, slice);
}
*out_ptr = map->ptr;
const struct intel_mipmap_tree *mt,
enum isl_format view_format, bool sampling,
struct brw_bo **clear_color_bo,
- uint32_t *clear_color_offset)
+ uint64_t *clear_color_offset)
{
assert(mt->aux_buf);
return mt->fast_clear_color;
}
}
+
+static void
+intel_miptree_update_etc_shadow(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice,
+ int level_w,
+ int level_h)
+{
+ ptrdiff_t etc_stride, shadow_stride;
+ void *mptr, *sptr;
+ struct intel_mipmap_tree *smt = mt->shadow_mt;
+
+ assert(intel_miptree_has_etc_shadow(brw, mt));
+
+ intel_miptree_map(brw, mt, level, slice, 0, 0, level_w, level_h,
+ GL_MAP_READ_BIT, &mptr, &etc_stride);
+ intel_miptree_map(brw, smt, level, slice, 0, 0, level_w, level_h,
+ GL_MAP_WRITE_BIT | GL_MAP_INVALIDATE_RANGE_BIT,
+ &sptr, &shadow_stride);
+
+ if (mt->format == MESA_FORMAT_ETC1_RGB8) {
+ _mesa_etc1_unpack_rgba8888(sptr, shadow_stride, mptr, etc_stride,
+ level_w, level_h);
+ } else {
+ /* destination and source images must have the same swizzle */
+ bool is_bgra = (smt->format == MESA_FORMAT_B8G8R8A8_SRGB);
+ _mesa_unpack_etc2_format(sptr, shadow_stride, mptr, etc_stride,
+ level_w, level_h, mt->format, is_bgra);
+ }
+
+ intel_miptree_unmap(brw, mt, level, slice);
+ intel_miptree_unmap(brw, smt, level, slice);
+}
+
+void
+intel_miptree_update_etc_shadow_levels(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ struct intel_mipmap_tree *smt;
+ int num_slices;
+
+ assert(mt);
+ assert(mt->surf.size_B > 0);
+ assert(intel_miptree_has_etc_shadow(brw, mt));
+
+ smt = mt->shadow_mt;
+ num_slices = smt->surf.logical_level0_px.array_len;
+
+ for (int level = smt->first_level; level <= smt->last_level; level++) {
+ int level_w = minify(smt->surf.logical_level0_px.width,
+ level - smt->first_level);
+ int level_h = minify(smt->surf.logical_level0_px.height,
+ level - smt->first_level);
+
+ for (unsigned int slice = 0; slice < num_slices; slice++) {
+ intel_miptree_update_etc_shadow(brw, mt, level, slice, level_w,
+ level_h);
+ }
+ }
+
+ mt->shadow_needs_update = false;
+}
projects / mesa.git / blobdiff