-/**************************************************************************
- *
+/*
* Copyright 2006 VMware, Inc.
* All Rights Reserved.
*
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
+ * distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
+ */
#include <GL/gl.h>
#include <GL/internal/dri_interface.h>
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
+static void *intel_miptree_map_raw(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+
+static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt);
+
static bool
intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
* created, based on the chip generation and the surface type.
*/
static enum intel_msaa_layout
-compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target,
+compute_msaa_layout(struct brw_context *brw, mesa_format format,
bool disable_aux_buffers)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
* by half the block width, and Y coordinates by half the block height.
*/
void
-intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
unsigned *width_px, unsigned *height)
{
switch (mt->tiling) {
}
}
+bool
+intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling)
+{
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "Fast Color Clear" bullet (p326):
+ *
+ * - Support is limited to tiled render targets.
+ *
+ * Gen9 changes the restriction to Y-tile only.
+ */
+ if (brw->gen >= 9)
+ return tiling == I915_TILING_Y;
+ else if (brw->gen >= 7)
+ return tiling != I915_TILING_NONE;
+ else
+ return false;
+}
/**
* For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
- * can be used.
+ * can be used. This doesn't (and should not) inspect any of the properties of
+ * the miptree's BO.
*
* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
* beneath the "Fast Color Clear" bullet (p326):
*
- * - Support is limited to tiled render targets.
* - Support is for non-mip-mapped and non-array surface types only.
*
* And then later, on p327:
* 64bpp, and 128bpp.
*/
bool
-intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+intel_miptree_is_fast_clear_capable(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
{
/* MCS support does not exist prior to Gen7 */
if (brw->gen < 7)
return false;
}
- if (mt->tiling != I915_TILING_X &&
- mt->tiling != I915_TILING_Y)
- return false;
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
return false;
if (mt->first_level != 0 || mt->last_level != 0) {
GLuint width0,
GLuint height0,
GLuint depth0,
- bool for_bo,
GLuint num_samples,
- enum intel_miptree_tiling_mode requested,
- bool force_all_slices_at_each_lod,
- bool disable_aux_buffers)
+ uint32_t layout_flags)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__,
- _mesa_lookup_enum_by_nr(target),
+ _mesa_enum_to_string(target),
_mesa_get_format_name(format),
first_level, last_level, depth0, mt);
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
- mt->disable_aux_buffers = disable_aux_buffers;
+ mt->disable_aux_buffers = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0;
exec_list_make_empty(&mt->hiz_map);
-
- /* The cpp is bytes per (1, blockheight)-sized block for compressed
- * textures. This is why you'll see divides by blockheight all over
- */
- unsigned bw, bh;
- _mesa_get_format_block_size(format, &bw, &bh);
- assert(_mesa_get_format_bytes(mt->format) % bw == 0);
- mt->cpp = _mesa_get_format_bytes(mt->format) / bw;
-
+ mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
mt->compressed = _mesa_is_format_compressed(format);
mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
mt->msaa_layout = compute_msaa_layout(brw, format,
- mt->target, mt->disable_aux_buffers);
+ mt->disable_aux_buffers);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
mt->physical_height0 = height0;
mt->physical_depth0 = depth0;
- if (!for_bo &&
+ if (!(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
(brw->has_separate_stencil &&
intel_miptree_wants_hiz_buffer(brw, mt)))) {
- const bool force_all_slices_at_each_lod = brw->gen == 6;
+ uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
+ if (brw->gen == 6) {
+ stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD |
+ MIPTREE_LAYOUT_TILING_ANY;
+ }
+
mt->stencil_mt = intel_miptree_create(brw,
mt->target,
MESA_FORMAT_S_UINT8,
mt->logical_width0,
mt->logical_height0,
mt->logical_depth0,
- true,
num_samples,
- INTEL_MIPTREE_TILING_ANY,
- force_all_slices_at_each_lod);
+ stencil_flags);
+
if (!mt->stencil_mt) {
intel_miptree_release(&mt);
return NULL;
}
}
- if (force_all_slices_at_each_lod)
+ if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
- brw_miptree_layout(brw, for_bo, requested, mt);
-
- if (mt->disable_aux_buffers)
- assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
-
- return mt;
-}
-
-/**
- * \brief Helper function for intel_miptree_create().
- */
-uint32_t
-intel_miptree_choose_tiling(struct brw_context *brw,
- mesa_format format,
- uint32_t width0,
- uint32_t num_samples,
- enum intel_miptree_tiling_mode requested,
- struct intel_mipmap_tree *mt)
-{
- if (format == MESA_FORMAT_S_UINT8) {
- /* The stencil buffer is W tiled. However, we request from the kernel a
- * non-tiled buffer because the GTT is incapable of W fencing.
- */
- return I915_TILING_NONE;
- }
-
- /* Some usages may want only one type of tiling, like depth miptrees (Y
- * tiled), or temporary BOs for uploading data once (linear).
- */
- switch (requested) {
- case INTEL_MIPTREE_TILING_ANY:
- break;
- case INTEL_MIPTREE_TILING_Y:
- return I915_TILING_Y;
- case INTEL_MIPTREE_TILING_NONE:
- return I915_TILING_NONE;
- }
-
- if (num_samples > 1) {
- /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
- * Surface"):
- *
- * [DevSNB+]: For multi-sample render targets, this field must be
- * 1. MSRTs can only be tiled.
- *
- * Our usual reason for preferring X tiling (fast blits using the
- * blitting engine) doesn't apply to MSAA, since we'll generally be
- * downsampling or upsampling when blitting between the MSAA buffer
- * and another buffer, and the blitting engine doesn't support that.
- * So use Y tiling, since it makes better use of the cache.
- */
- return I915_TILING_Y;
- }
-
- GLenum base_format = _mesa_get_format_base_format(format);
- if (base_format == GL_DEPTH_COMPONENT ||
- base_format == GL_DEPTH_STENCIL_EXT)
- return I915_TILING_Y;
-
- /* 1D textures (and 1D array textures) don't get any benefit from tiling,
- * in fact it leads to a less efficient use of memory space and bandwidth
- * due to tile alignment.
+ /*
+ * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
+ * multisampled or have an AUX buffer attached to it.
+ *
+ * GEN | MSRT | AUX_CCS_* or AUX_MCS
+ * -------------------------------------------
+ * 9 | HALIGN_16 | HALIGN_16
+ * 8 | HALIGN_ANY | HALIGN_16
+ * 7 | ? | ?
+ * 6 | ? | ?
*/
- if (mt->logical_height0 == 1)
- return I915_TILING_NONE;
-
- int minimum_pitch = mt->total_width * mt->cpp;
-
- /* If the width is much smaller than a tile, don't bother tiling. */
- if (minimum_pitch < 64)
- return I915_TILING_NONE;
-
- if (ALIGN(minimum_pitch, 512) >= 32768 ||
- mt->total_width >= 32768 || mt->total_height >= 32768) {
- perf_debug("%dx%d miptree too large to blit, falling back to untiled",
- mt->total_width, mt->total_height);
- return I915_TILING_NONE;
+ if (intel_miptree_is_fast_clear_capable(brw, mt)) {
+ if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1))
+ layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+ } else if (brw->gen >= 9 && num_samples > 1) {
+ layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+ } else {
+ /* For now, nothing else has this requirement */
+ assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
}
- /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
- if (brw->gen < 6)
- return I915_TILING_X;
-
- /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
- * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
- * or Linear."
- * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
- * all the way back to 965, but is permitted on Gen7+.
- */
- if (brw->gen < 7 && mt->cpp >= 16)
- return I915_TILING_X;
+ brw_miptree_layout(brw, mt, layout_flags);
- /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
- * messages), on p64, under the heading "Surface Vertical Alignment":
- *
- * This field must be set to VALIGN_4 for all tiled Y Render Target
- * surfaces.
- *
- * So if the surface is renderable and uses a vertical alignment of 2,
- * force it to be X tiled. This is somewhat conservative (it's possible
- * that the client won't ever render to this surface), but it's difficult
- * to know that ahead of time. And besides, since we use a vertical
- * alignment of 4 as often as we can, this shouldn't happen very often.
- */
- if (brw->gen == 7 && mt->align_h == 2 &&
- brw->format_supported_as_render_target[format]) {
- return I915_TILING_X;
- }
+ if (mt->disable_aux_buffers)
+ assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
- return I915_TILING_Y | I915_TILING_X;
+ return mt;
}
}
}
+/* This function computes Yf/Ys tiled bo size, alignment and pitch. */
+static unsigned long
+intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt, unsigned *alignment,
+ unsigned long *pitch)
+{
+ uint32_t tile_width, tile_height;
+ unsigned long stride, size, aligned_y;
+
+ assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);
+ intel_get_tile_dims(mt->tiling, mt->tr_mode, mt->cpp,
+ &tile_width, &tile_height);
+
+ aligned_y = ALIGN(mt->total_height, tile_height);
+ stride = mt->total_width * mt->cpp;
+ stride = ALIGN(stride, tile_width);
+ size = stride * aligned_y;
+
+ if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YF) {
+ assert(size % 4096 == 0);
+ *alignment = 4096;
+ } else {
+ assert(size % (64 * 1024) == 0);
+ *alignment = 64 * 1024;
+ }
+ *pitch = stride;
+ return size;
+}
struct intel_mipmap_tree *
intel_miptree_create(struct brw_context *brw,
GLuint width0,
GLuint height0,
GLuint depth0,
- bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode requested_tiling,
- bool force_all_slices_at_each_lod)
+ uint32_t layout_flags)
{
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
mesa_format etc_format = MESA_FORMAT_NONE;
GLuint total_width, total_height;
+ uint32_t alloc_flags = 0;
format = intel_lower_compressed_format(brw, format);
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
+ assert((layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) == 0);
+ assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
mt = intel_miptree_create_layout(brw, target, format,
- first_level, last_level, width0,
- height0, depth0,
- false, num_samples,
- requested_tiling,
- force_all_slices_at_each_lod,
- false /*disable_aux_buffers*/);
-
- if (!mt)
+ first_level, last_level, width0,
+ height0, depth0, num_samples,
+ layout_flags);
+ /*
+ * pitch == 0 || height == 0 indicates the null texture
+ */
+ if (!mt || !mt->total_width || !mt->total_height) {
+ intel_miptree_release(&mt);
return NULL;
+ }
total_width = mt->total_width;
total_height = mt->total_height;
mt->tiling = I915_TILING_Y;
}
+ if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
+ alloc_flags |= BO_ALLOC_FOR_RENDER;
+
unsigned long pitch;
mt->etc_format = etc_format;
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
- total_width, total_height, mt->cpp,
- &mt->tiling, &pitch,
- (expect_accelerated_upload ?
- BO_ALLOC_FOR_RENDER : 0));
+
+ if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
+ unsigned alignment = 0;
+ unsigned long size;
+ size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch);
+ assert(size);
+ mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree",
+ size, alignment);
+ } else {
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ total_width, total_height, mt->cpp,
+ &mt->tiling, &pitch,
+ alloc_flags);
+ }
+
mt->pitch = pitch;
/* If the BO is too large to fit in the aperture, we need to use the
mt->tiling = I915_TILING_X;
drm_intel_bo_unreference(mt->bo);
mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
- total_width, total_height, mt->cpp,
- &mt->tiling, &pitch,
- (expect_accelerated_upload ?
- BO_ALLOC_FOR_RENDER : 0));
+ total_width, total_height, mt->cpp,
+ &mt->tiling, &pitch, alloc_flags);
mt->pitch = pitch;
}
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ assert(mt->num_samples > 1);
if (!intel_miptree_alloc_mcs(brw, mt, num_samples)) {
intel_miptree_release(&mt);
return NULL;
* Allocation of the MCS miptree will be deferred until the first fast
* clear actually occurs.
*/
- if (intel_is_non_msrt_mcs_buffer_supported(brw, mt))
+ if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
+ intel_miptree_is_fast_clear_capable(brw, mt)) {
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
+ assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
+ }
return mt;
}
uint32_t height,
uint32_t depth,
int pitch,
- bool disable_aux_buffers)
+ uint32_t layout_flags)
{
struct intel_mipmap_tree *mt;
uint32_t tiling, swizzle;
target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
- /* 'requested' parameter of intel_miptree_create_layout() is relevant
- * only for non bo miptree. Tiling for bo is already computed above.
- * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is
- * just a place holder and will not make any change to the miptree
- * tiling format.
+ /* The BO already has a tiling format and we shouldn't confuse the lower
+ * layers by making it try to find a tiling format again.
*/
+ assert((layout_flags & MIPTREE_LAYOUT_TILING_ANY) == 0);
+ assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);
+
+ layout_flags |= MIPTREE_LAYOUT_FOR_BO;
mt = intel_miptree_create_layout(brw, target, format,
0, 0,
- width, height, depth,
- true, 0,
- INTEL_MIPTREE_TILING_ANY,
- false,
- disable_aux_buffers);
+ width, height, depth, 0,
+ layout_flags);
if (!mt)
return NULL;
height,
1,
pitch,
- false);
+ 0);
if (!singlesample_mt)
goto fail;
* Allocation of the MCS miptree will be deferred until the first fast
* clear actually occurs.
*/
- if (intel_is_non_msrt_mcs_buffer_supported(intel, singlesample_mt))
+ if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) &&
+ intel_miptree_is_fast_clear_capable(intel, singlesample_mt))
singlesample_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
if (num_samples == 0) {
uint32_t depth = 1;
bool ok;
GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
+ const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
+ MIPTREE_LAYOUT_TILING_ANY;
+
mt = intel_miptree_create(brw, target, format, 0, 0,
- width, height, depth, true, num_samples,
- INTEL_MIPTREE_TILING_ANY, false);
+ width, height, depth, num_samples,
+ layout_flags);
if (!mt)
goto fail;
*mt = NULL;
}
+
void
-intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
- int *width, int *height, int *depth)
+intel_get_image_dims(struct gl_texture_image *image,
+ int *width, int *height, int *depth)
{
switch (image->TexObject->Target) {
case GL_TEXTURE_1D_ARRAY:
+ /* For a 1D Array texture the OpenGL API will treat the image height as
+ * the number of array slices. For Intel hardware, we treat the 1D array
+ * as a 2D Array with a height of 1. So, here we want to swap image
+ * height and depth.
+ */
*width = image->Width;
*height = 1;
*depth = image->Height;
if (image->TexFormat != mt_format)
return false;
- intel_miptree_get_dimensions_for_image(image, &width, &height, &depth);
+ intel_get_image_dims(image, &width, &height, &depth);
if (mt->target == GL_TEXTURE_CUBE_MAP)
depth = 6;
*y = mt->level[level].slice[slice].y_offset;
}
+
+/**
+ * This function computes the tile_w (in bytes) and tile_h (in rows) of
+ * different tiling patterns. If the BO is untiled, tile_w is set to cpp
+ * and tile_h is set to 1.
+ */
+void
+intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+ uint32_t *tile_w, uint32_t *tile_h)
+{
+ if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) {
+ switch (tiling) {
+ case I915_TILING_X:
+ *tile_w = 512;
+ *tile_h = 8;
+ break;
+ case I915_TILING_Y:
+ *tile_w = 128;
+ *tile_h = 32;
+ break;
+ case I915_TILING_NONE:
+ *tile_w = cpp;
+ *tile_h = 1;
+ break;
+ default:
+ unreachable("not reached");
+ }
+ } else {
+ uint32_t aspect_ratio = 1;
+ assert(_mesa_is_pow_two(cpp));
+
+ switch (cpp) {
+ case 1:
+ *tile_h = 64;
+ break;
+ case 2:
+ case 4:
+ *tile_h = 32;
+ break;
+ case 8:
+ case 16:
+ *tile_h = 16;
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+ if (cpp == 2 || cpp == 8)
+ aspect_ratio = 2;
+
+ if (tr_mode == INTEL_MIPTREE_TRMODE_YS)
+ *tile_h *= 4;
+
+ *tile_w = *tile_h * aspect_ratio * cpp;
+ }
+}
+
+
/**
* This function computes masks that may be used to select the bits of the X
* and Y coordinates that indicate the offset within a tile. If the BO is
* untiled, the masks are set to 0.
*/
void
-intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
- uint32_t *mask_x, uint32_t *mask_y,
- bool map_stencil_as_y_tiled)
+intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+ bool map_stencil_as_y_tiled,
+ uint32_t *mask_x, uint32_t *mask_y)
{
- int cpp = mt->cpp;
- uint32_t tiling = mt->tiling;
-
+ uint32_t tile_w_bytes, tile_h;
if (map_stencil_as_y_tiled)
tiling = I915_TILING_Y;
- switch (tiling) {
- default:
- unreachable("not reached");
- case I915_TILING_NONE:
- *mask_x = *mask_y = 0;
- break;
- case I915_TILING_X:
- *mask_x = 512 / cpp - 1;
- *mask_y = 7;
- break;
- case I915_TILING_Y:
- *mask_x = 128 / cpp - 1;
- *mask_y = 31;
- break;
- }
+ intel_get_tile_dims(tiling, tr_mode, cpp, &tile_w_bytes, &tile_h);
+
+ *mask_x = tile_w_bytes / cpp - 1;
+ *mask_y = tile_h - 1;
}
/**
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, false);
+ intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, false, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
assert(src_mt->format == dst_mt->format);
if (dst_mt->compressed) {
- height = ALIGN(height, dst_mt->align_h) / dst_mt->align_h;
- width = ALIGN(width, dst_mt->align_w);
+ unsigned int i, j;
+ _mesa_get_format_block_size(dst_mt->format, &i, &j);
+ height = ALIGN_NPOT(height, j) / j;
+ width = ALIGN_NPOT(width, i) / i;
}
/* If it's a packed depth/stencil buffer with separate stencil, the blit
*
* "The MCS surface must be stored as Tile Y."
*/
+ const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
+ MIPTREE_LAYOUT_TILING_Y;
mt->mcs_mt = intel_miptree_create(brw,
mt->target,
format,
mt->logical_width0,
mt->logical_height0,
mt->logical_depth0,
- true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_Y,
- false);
+ mcs_flags);
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
*/
void *data = intel_miptree_map_raw(brw, mt->mcs_mt);
memset(data, 0xff, mt->mcs_mt->total_height * mt->mcs_mt->pitch);
- intel_miptree_unmap_raw(brw, mt->mcs_mt);
+ intel_miptree_unmap_raw(mt->mcs_mt);
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
return mt->mcs_mt;
const mesa_format format = MESA_FORMAT_R_UINT32;
unsigned block_width_px;
unsigned block_height;
- intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height);
+ intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height);
unsigned width_divisor = block_width_px * 4;
unsigned height_divisor = block_height * 8;
unsigned mcs_width =
unsigned mcs_height =
ALIGN(mt->logical_height0, height_divisor) / height_divisor;
assert(mt->logical_depth0 == 1);
+ uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
+ MIPTREE_LAYOUT_TILING_Y;
+ if (brw->gen >= 8) {
+ layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+ }
mt->mcs_mt = intel_miptree_create(brw,
mt->target,
format,
mcs_width,
mcs_height,
mt->logical_depth0,
- true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_Y,
- false);
+ layout_flags);
return mt->mcs_mt;
}
unsigned H_i = H0;
unsigned Z_i = Z0;
hz_height = 0;
- for (int level = mt->first_level; level <= mt->last_level; ++level) {
+ for (unsigned level = mt->first_level; level <= mt->last_level; ++level) {
unsigned h_i = ALIGN(H_i, vertical_align);
/* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
hz_height += h_i * Z_i;
/* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
* adjustments required for Z_Height and Z_Width based on multisampling.
*/
- switch (mt->num_samples) {
- case 0:
- case 1:
- break;
- case 2:
- case 4:
- z_width *= 2;
- z_height *= 2;
- break;
- case 8:
- z_width *= 4;
- z_height *= 2;
- break;
- default:
- unreachable("unsupported sample count");
+ if (brw->gen < 9) {
+ switch (mt->num_samples) {
+ case 0:
+ case 1:
+ break;
+ case 2:
+ case 4:
+ z_width *= 2;
+ z_height *= 2;
+ break;
+ case 8:
+ z_width *= 4;
+ z_height *= 2;
+ break;
+ default:
+ unreachable("unsupported sample count");
+ }
}
const unsigned vertical_align = 8; /* 'j' in the docs */
unsigned Z_i = Z0;
unsigned sum_h_i = 0;
unsigned hz_height_3d_sum = 0;
- for (int level = mt->first_level; level <= mt->last_level; ++level) {
+ for (unsigned level = mt->first_level; level <= mt->last_level; ++level) {
unsigned i = level - mt->first_level;
unsigned h_i = ALIGN(H_i, vertical_align);
/* sum(i=2 to m; h_i) */
struct intel_mipmap_tree *mt)
{
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
- const bool force_all_slices_at_each_lod = brw->gen == 6;
+ uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
+
+ if (brw->gen == 6)
+ layout_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD;
if (!buf)
return NULL;
+ layout_flags |= MIPTREE_LAYOUT_TILING_ANY;
buf->mt = intel_miptree_create(brw,
mt->target,
mt->format,
mt->logical_width0,
mt->logical_height0,
mt->logical_depth0,
- true,
mt->num_samples,
- INTEL_MIPTREE_TILING_ANY,
- force_all_slices_at_each_lod);
+ layout_flags);
if (!buf->mt) {
free(buf);
return NULL;
return false;
/* Mark that all slices need a HiZ resolve. */
- for (int level = mt->first_level; level <= mt->last_level; ++level) {
+ for (unsigned level = mt->first_level; level <= mt->last_level; ++level) {
if (!intel_miptree_level_enable_hiz(brw, mt, level))
continue;
- for (int layer = 0; layer < mt->level[level].depth; ++layer) {
+ for (unsigned layer = 0; layer < mt->level[level].depth; ++layer) {
struct intel_resolve_map *m = malloc(sizeof(struct intel_resolve_map));
exec_node_init(&m->link);
m->level = level;
}
void
-intel_miptree_unmap_raw(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+intel_miptree_unmap_raw(struct intel_mipmap_tree *mt)
{
drm_intel_bo_unmap(mt->bo);
}
*/
_mesa_get_format_block_size(mt->format, &bw, &bh);
assert(y % bh == 0);
+ assert(x % bw == 0);
y /= bh;
+ x /= bw;
base = intel_miptree_map_raw(brw, mt) + mt->offset;
}
static void
-intel_miptree_unmap_gtt(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- struct intel_miptree_map *map,
- unsigned int level,
- unsigned int slice)
+intel_miptree_unmap_gtt(struct intel_mipmap_tree *mt)
{
- intel_miptree_unmap_raw(brw, mt);
+ intel_miptree_unmap_raw(mt);
}
static void
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
{
- map->mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
- 0, 0,
- map->w, map->h, 1,
- false, 0,
- INTEL_MIPTREE_TILING_NONE,
- false);
- if (!map->mt) {
+ map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
+ /* first_level */ 0,
+ /* last_level */ 0,
+ map->w, map->h, 1,
+ /* samples */ 0,
+ MIPTREE_LAYOUT_TILING_NONE);
+
+ if (!map->linear_mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
goto fail;
}
- map->stride = map->mt->pitch;
+ map->stride = map->linear_mt->pitch;
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
if (!intel_miptree_blit(brw,
mt, level, slice,
map->x, map->y, false,
- map->mt, 0, 0,
+ map->linear_mt, 0, 0,
0, 0, false,
map->w, map->h, GL_COPY)) {
fprintf(stderr, "Failed to blit\n");
}
}
- map->ptr = intel_miptree_map_raw(brw, map->mt);
+ map->ptr = intel_miptree_map_raw(brw, map->linear_mt);
DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
return;
fail:
- intel_miptree_release(&map->mt);
+ intel_miptree_release(&map->linear_mt);
map->ptr = NULL;
map->stride = 0;
}
{
struct gl_context *ctx = &brw->ctx;
- intel_miptree_unmap_raw(brw, map->mt);
+ intel_miptree_unmap_raw(map->linear_mt);
if (map->mode & GL_MAP_WRITE_BIT) {
bool ok = intel_miptree_blit(brw,
- map->mt, 0, 0,
+ map->linear_mt, 0, 0,
0, 0, false,
mt, level, slice,
map->x, map->y, false,
WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
}
- intel_miptree_release(&map->mt);
+ intel_miptree_release(&map->linear_mt);
}
/**
_mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes);
}
- intel_miptree_unmap_raw(brw, mt);
+ intel_miptree_unmap_raw(mt);
}
static void
}
}
- intel_miptree_unmap_raw(brw, mt);
+ intel_miptree_unmap_raw(mt);
DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
}
}
- intel_miptree_unmap_raw(brw, mt);
+ intel_miptree_unmap_raw(mt);
}
free(map->buffer);
map->ptr, map->stride,
map->w, map->h, mt->etc_format);
- intel_miptree_unmap_raw(brw, mt);
+ intel_miptree_unmap_raw(mt);
free(map->buffer);
}
}
}
- intel_miptree_unmap_raw(brw, s_mt);
- intel_miptree_unmap_raw(brw, z_mt);
+ intel_miptree_unmap_raw(s_mt);
+ intel_miptree_unmap_raw(z_mt);
DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
__func__,
}
}
- intel_miptree_unmap_raw(brw, s_mt);
- intel_miptree_unmap_raw(brw, z_mt);
+ intel_miptree_unmap_raw(s_mt);
+ intel_miptree_unmap_raw(z_mt);
DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
__func__,
} else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
#if defined(USE_SSE41)
- } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
+ } else if (!(mode & GL_MAP_WRITE_BIT) &&
+ !mt->compressed && cpu_has_sse4_1 &&
+ (mt->pitch % 16 == 0)) {
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {
intel_miptree_unmap_etc(brw, mt, map, level, slice);
} else if (mt->stencil_mt && !(map->mode & BRW_MAP_DIRECT_BIT)) {
intel_miptree_unmap_depthstencil(brw, mt, map, level, slice);
- } else if (map->mt) {
+ } else if (map->linear_mt) {
intel_miptree_unmap_blit(brw, mt, map, level, slice);
#if defined(USE_SSE41)
} else if (map->buffer && cpu_has_sse4_1) {
intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);
#endif
} else {
- intel_miptree_unmap_gtt(brw, mt, map, level, slice);
+ intel_miptree_unmap_gtt(mt);
}
intel_miptree_release_map(mt, level, slice);
projects / mesa.git / blobdiff