i965: Add and use a single miptree aux_buf field

[mesa.git] / src / mesa / drivers / dri / i965 / intel_mipmap_tree.h

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8fe5c4add671f8741ee2e2e8efa146a5733f9503..241832f686f4429e7242cbab6771363f425547ae 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -272,16 +272,6 @@ struct intel_mipmap_tree
     */
    uint32_t offset;
 
-   /**
-    * \brief HiZ aux buffer
-    *
-    * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
-    *
-    * To determine if hiz is enabled, do not check this pointer. Instead, use
-    * intel_miptree_level_has_hiz().
-    */
-   struct intel_miptree_aux_buffer *hiz_buf;
-
    /**
     * \brief The type of auxiliary compression used by this miptree.
     *
@@ -335,15 +325,29 @@ struct intel_mipmap_tree
    bool r8stencil_needs_update;
 
    /**
-    * \brief MCS auxiliary buffer.
+    * \brief CCS, MCS, or HiZ auxiliary buffer.
+    *
+    * NULL if no auxiliary buffer is in use for this surface.
     *
-    * This buffer contains the "multisample control surface", which stores
-    * the necessary information to implement compressed MSAA
-    * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
+    * For single-sampled color miptrees:
+    *    This buffer contains the Color Control Surface, which stores the
+    *    necessary information to implement lossless color compression (CCS_E)
+    *    and "fast color clear" (CCS_D) behaviour.
     *
-    * NULL if no MCS buffer is in use for this surface.
+    * For multi-sampled color miptrees:
+    *    This buffer contains the Multisample Control Surface, which stores the
+    *    necessary information to implement compressed MSAA
+    *    (INTEL_MSAA_FORMAT_CMS).
+    *
+    * For depth miptrees:
+    *    This buffer contains the Hierarchical Depth Buffer, which stores the
+    *    necessary information to implement lossless depth compression and fast
+    *    depth clear behavior.
+    *
+    *    To determine if HiZ is enabled, do not check this pointer. Instead,
+    *    use intel_miptree_level_has_hiz().
     */
-   struct intel_miptree_aux_buffer *mcs_buf;
+   struct intel_miptree_aux_buffer *aux_buf;
 
    /**
     * Planes 1 and 2 in case this is a planar surface.
@@ -485,23 +489,6 @@ enum isl_dim_layout
 get_isl_dim_layout(const struct gen_device_info *devinfo,
                    enum isl_tiling tiling, GLenum target);
 
-static inline struct intel_miptree_aux_buffer *
-intel_miptree_get_aux_buffer(const struct intel_mipmap_tree *mt)
-{
-   switch (mt->aux_usage) {
-   case ISL_AUX_USAGE_MCS:
-   case ISL_AUX_USAGE_CCS_D:
-   case ISL_AUX_USAGE_CCS_E:
-      return mt->mcs_buf;
-   case ISL_AUX_USAGE_HIZ:
-      return mt->hiz_buf;
-   case ISL_AUX_USAGE_NONE:
-      return NULL;
-   default:
-      unreachable("Invalid aux_usage!\n");
-   }
-}
-
 void
 intel_get_image_dims(struct gl_texture_image *image,
                      int *width, int *height, int *depth);