i965: Enable regular fast-clears (CCS_D) on gen9+

[mesa.git] / src / mesa / drivers / dri / i965 / intel_mipmap_tree.h

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 4a5fed2091ee63272b9e42a63e9d6fb49827ec86..3628345c4e940e3c8c79011fd065afff0ec559e4 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -545,7 +545,8 @@ intel_miptree_prepare_access(struct brw_context *brw,
                              struct intel_mipmap_tree *mt,
                              uint32_t start_level, uint32_t num_levels,
                              uint32_t start_layer, uint32_t num_layers,
-                             bool aux_supported, bool fast_clear_supported);
+                             enum isl_aux_usage aux_usage,
+                             bool fast_clear_supported);
 
 /** Complete a write operation
  *
@@ -571,7 +572,7 @@ void
 intel_miptree_finish_write(struct brw_context *brw,
                            struct intel_mipmap_tree *mt, uint32_t level,
                            uint32_t start_layer, uint32_t num_layers,
-                           bool written_with_aux);
+                           enum isl_aux_usage aux_usage);
 
 /** Get the auxiliary compression state of a miptree slice */
 enum isl_aux_state
@@ -610,10 +611,14 @@ intel_miptree_access_raw(struct brw_context *brw,
       intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 }
 
+enum isl_aux_usage
+intel_miptree_texture_aux_usage(struct brw_context *brw,
+                                struct intel_mipmap_tree *mt,
+                                enum isl_format view_format);
 void
 intel_miptree_prepare_texture(struct brw_context *brw,
                               struct intel_mipmap_tree *mt,
-                              mesa_format view_format,
+                              enum isl_format view_format,
                               bool *aux_supported_out);
 void
 intel_miptree_prepare_image(struct brw_context *brw,
@@ -622,15 +627,20 @@ void
 intel_miptree_prepare_fb_fetch(struct brw_context *brw,
                                struct intel_mipmap_tree *mt, uint32_t level,
                                uint32_t start_layer, uint32_t num_layers);
+enum isl_aux_usage
+intel_miptree_render_aux_usage(struct brw_context *brw,
+                               struct intel_mipmap_tree *mt,
+                               bool srgb_enabled, bool blend_enabled);
 void
 intel_miptree_prepare_render(struct brw_context *brw,
                              struct intel_mipmap_tree *mt, uint32_t level,
                              uint32_t start_layer, uint32_t layer_count,
-                             bool srgb_enabled);
+                             bool srgb_enabled, bool blend_enabled);
 void
 intel_miptree_finish_render(struct brw_context *brw,
                             struct intel_mipmap_tree *mt, uint32_t level,
-                            uint32_t start_layer, uint32_t layer_count);
+                            uint32_t start_layer, uint32_t layer_count,
+                            bool srgb_enabled, bool blend_enabled);
 void
 intel_miptree_prepare_depth(struct brw_context *brw,
                             struct intel_mipmap_tree *mt, uint32_t level,