* The hardware has a fixed layout of a texture depending on parameters such
* as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
* mipmap levels. The individual level/layer slices are each 2D rectangles of
- * pixels at some x/y offset from the start of the drm_intel_bo.
+ * pixels at some x/y offset from the start of the brw_bo.
*
* Original OpenGL allowed texture miplevels to be specified in arbitrary
* order, and a texture may change size over time. Thus, each
#include <assert.h>
#include "main/mtypes.h"
-#include "intel_bufmgr.h"
-#include "intel_resolve_map.h"
+#include "isl/isl.h"
+#include "blorp/blorp.h"
+#include "brw_bufmgr.h"
#include <GL/internal/dri_interface.h>
#ifdef __cplusplus
struct brw_context;
struct intel_renderbuffer;
-struct intel_resolve_map;
struct intel_texture_image;
/**
+ * This bit extends the set of GL_MAP_*_BIT enums.
+ *
* When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
* depthstencil-split-to-separate-stencil miptree, we'll normally make a
- * tmeporary and recreate the kind of data requested by Mesa core, since we're
+ * temporary and recreate the kind of data requested by Mesa core, since we're
* satisfying some glGetTexImage() request or something.
*
* However, occasionally you want to actually map the miptree's current data
#define BRW_MAP_DIRECT_BIT 0x80000000
struct intel_miptree_map {
- /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
+ /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
GLbitfield mode;
/** Region of interest for the map. */
int x, y, w, h;
/** Possibly malloced temporary buffer for the mapping. */
void *buffer;
/** Possible pointer to a temporary linear miptree for the mapping. */
- struct intel_mipmap_tree *mt;
+ struct intel_mipmap_tree *linear_mt;
/** Pointer to the start of (map_x, map_y) returned by the mapping. */
void *ptr;
/** Stride of the mapping. */
/** Offset to this miptree level, used in computing y_offset. */
GLuint level_y;
- /**
- * \brief Number of 2D slices in this miplevel.
- *
- * The exact semantics of depth varies according to the texture target:
- * - For GL_TEXTURE_CUBE_MAP, depth is 6.
- * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
- * identical for all miplevels in the texture.
- * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
- * value, like width and height, varies with miplevel.
- * - For other texture types, depth is 1.
- * - Additionally, for UMS and CMS miptrees, depth is multiplied by
- * sample count.
- */
- GLuint depth;
-
/**
* \brief Is HiZ enabled for this level?
*
* layers in a 3D texture. The list's length is \c depth.
*/
struct intel_mipmap_slice {
- /**
- * \name Offset to slice
- * \{
- *
- * Hardware formats are so diverse that that there is no unified way to
- * compute the slice offsets, so we store them in this table.
- *
- * The (x, y) offset to slice \c s at level \c l relative the miptrees
- * base address is
- * \code
- * x = mt->level[l].slice[s].x_offset
- * y = mt->level[l].slice[s].y_offset
- */
- GLuint x_offset;
- GLuint y_offset;
- /** \} */
-
/**
* Mapping information. Persistent for the duration of
* intel_miptree_map/unmap on this slice.
};
/**
- * Enum for keeping track of the different MSAA layouts supported by Gen7.
- */
-enum intel_msaa_layout
-{
- /**
- * Ordinary surface with no MSAA.
- */
- INTEL_MSAA_LAYOUT_NONE,
-
- /**
- * Interleaved Multisample Surface. The additional samples are
- * accommodated by scaling up the width and the height of the surface so
- * that all the samples corresponding to a pixel are located at nearby
- * memory locations.
- */
- INTEL_MSAA_LAYOUT_IMS,
-
- /**
- * Uncompressed Multisample Surface. The surface is stored as a 2D array,
- * with array slice n containing all pixel data for sample n.
- */
- INTEL_MSAA_LAYOUT_UMS,
-
- /**
- * Compressed Multisample Surface. The surface is stored as in
- * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
- * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
- * indicates the mapping from sample number to array slice. This allows
- * the common case (where all samples constituting a pixel have the same
- * color value) to be stored efficiently by just using a single array
- * slice.
- */
- INTEL_MSAA_LAYOUT_CMS,
-};
-
-
-/**
- * Enum for keeping track of the fast clear state of a buffer associated with
- * a miptree.
- *
- * Fast clear works by deferring the memory writes that would be used to clear
- * the buffer, so that instead of performing them at the time of the clear
- * operation, the hardware automatically performs them at the time that the
- * buffer is later accessed for rendering. The MCS buffer keeps track of
- * which regions of the buffer still have pending clear writes.
- *
- * This enum keeps track of the driver's knowledge of pending fast clears in
- * the MCS buffer.
+ * Miptree aux buffer. These buffers are associated with a miptree, but the
+ * format is managed by the hardware.
*
- * MCS buffers only exist on Gen7+.
+ * For Gen7+, we always give the hardware the start of the buffer, and let it
+ * handle all accesses to the buffer. Therefore we don't need the full miptree
+ * layout structure for this buffer.
*/
-enum intel_fast_clear_state
+struct intel_miptree_aux_buffer
{
- /**
- * There is no MCS buffer for this miptree, and one should never be
- * allocated.
- */
- INTEL_FAST_CLEAR_STATE_NO_MCS,
+ struct isl_surf surf;
/**
- * No deferred clears are pending for this miptree, and the contents of the
- * color buffer are entirely correct. An MCS buffer may or may not exist
- * for this miptree. If it does exist, it is entirely in the "no deferred
- * clears pending" state. If it does not exist, it will be created the
- * first time a fast color clear is executed.
- *
- * In this state, the color buffer can be used for purposes other than
- * rendering without needing a render target resolve.
+ * Buffer object containing the pixel data.
*
- * Since there is no such thing as a "fast color clear resolve" for MSAA
- * buffers, an MSAA buffer will never be in this state.
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
*/
- INTEL_FAST_CLEAR_STATE_RESOLVED,
+ struct brw_bo *bo;
/**
- * An MCS buffer exists for this miptree, and deferred clears are pending
- * for some regions of the color buffer, as indicated by the MCS buffer.
- * The contents of the color buffer are only correct for the regions where
- * the MCS buffer doesn't indicate a deferred clear.
+ * Offset into bo where the surface starts.
*
- * If a single-sample buffer is in this state, a render target resolve must
- * be performed before it can be used for purposes other than rendering.
+ * @see intel_mipmap_aux_buffer::bo
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
*/
- INTEL_FAST_CLEAR_STATE_UNRESOLVED,
+ uint32_t offset;
- /**
- * An MCS buffer exists for this miptree, and deferred clears are pending
- * for the entire color buffer, and the contents of the MCS buffer reflect
- * this. The contents of the color buffer are undefined.
+ /*
+ * Size of the MCS surface.
*
- * If a single-sample buffer is in this state, a render target resolve must
- * be performed before it can be used for purposes other than rendering.
- *
- * If the client attempts to clear a buffer which is already in this state,
- * the clear can be safely skipped, since the buffer is already clear.
+ * This is needed when doing any gtt mapped operations on the buffer (which
+ * will be Y-tiled). It is possible that it will not be the same as bo->size
+ * when the drm allocator rounds up the requested size.
*/
- INTEL_FAST_CLEAR_STATE_CLEAR,
-};
+ size_t size;
-enum miptree_array_layout {
- /* Each array slice contains all miplevels packed together.
- *
- * Gen hardware usually wants multilevel miptrees configured this way.
- *
- * A 2D Array texture with 2 slices and multiple LODs using
- * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
+ /**
+ * Pitch in bytes.
*
- * +----------+
- * | |
- * | |
- * +----------+
- * +---+ +-+
- * | | +-+
- * +---+ *
- * +----------+
- * | |
- * | |
- * +----------+
- * +---+ +-+
- * | | +-+
- * +---+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
*/
- ALL_LOD_IN_EACH_SLICE,
+ uint32_t pitch;
- /* Each LOD contains all slices of that LOD packed together.
- *
- * In some situations, Gen7+ hardware can use the array_spacing_lod0
- * feature to save space when the surface only contains LOD 0.
- *
- * Gen6 uses this for separate stencil and hiz since gen6 does not support
- * multiple LODs for separate stencil and hiz.
- *
- * A 2D Array texture with 2 slices and multiple LODs using
- * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
+ /**
+ * The distance in rows between array slices.
*
- * +----------+
- * | |
- * | |
- * +----------+
- * | |
- * | |
- * +----------+
- * +---+ +-+
- * | | +-+
- * +---+ +-+
- * | | :
- * +---+
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
*/
- ALL_SLICES_AT_EACH_LOD,
-};
-
-/**
- * Miptree aux buffer. These buffers are associated with a miptree, but the
- * format is managed by the hardware.
- *
- * For Gen7+, we always give the hardware the start of the buffer, and let it
- * handle all accesses to the buffer. Therefore we don't need the full miptree
- * layout structure for this buffer.
- *
- * For Gen6, we need a hiz miptree structure for this buffer so we can program
- * offsets to slices & miplevels.
- */
-struct intel_miptree_aux_buffer
-{
- /** Buffer object containing the pixel data. */
- drm_intel_bo *bo;
-
- uint32_t pitch; /**< pitch in bytes. */
-
- uint32_t qpitch; /**< The distance in rows between array slices. */
-
- struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
-};
-
-/* Tile resource modes */
-enum intel_miptree_tr_mode {
- INTEL_MIPTREE_TRMODE_NONE,
- INTEL_MIPTREE_TRMODE_YF,
- INTEL_MIPTREE_TRMODE_YS
+ uint32_t qpitch;
};
struct intel_mipmap_tree
{
- /** Buffer object containing the pixel data. */
- drm_intel_bo *bo;
-
- uint32_t pitch; /**< pitch in bytes. */
+ struct isl_surf surf;
- uint32_t tiling; /**< One of the I915_TILING_* flags */
- enum intel_miptree_tr_mode tr_mode;
+ /**
+ * Buffer object containing the surface.
+ *
+ * @see intel_mipmap_tree::offset
+ * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
+ */
+ struct brw_bo *bo;
- /* Effectively the key:
+ /**
+ * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceType
+ * @see RENDER_SURFACE_STATE.SurfaceArray
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
*/
GLenum target;
*
* For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
* formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceFormat
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
*/
mesa_format format;
- /** This variable stores the value of ETC compressed texture format */
- mesa_format etc_format;
-
/**
- * The X offset of each image in the miptree must be aligned to this.
- * See the comments in brw_tex_layout.c.
+ * This variable stores the value of ETC compressed texture format
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceFormat
*/
- unsigned int align_w;
- unsigned int align_h; /**< \see align_w */
+ mesa_format etc_format;
GLuint first_level;
GLuint last_level;
- /**
- * Level zero image dimensions. These dimensions correspond to the
- * physical layout of data in memory. Accordingly, they account for the
- * extra width, height, and or depth that must be allocated in order to
- * accommodate multisample formats, and they account for the extra factor
- * of 6 in depth that must be allocated in order to accommodate cubemap
- * textures.
- */
- GLuint physical_width0, physical_height0, physical_depth0;
+ /** Bytes per pixel (or bytes per block if compressed) */
+ GLuint cpp;
- GLuint cpp; /**< bytes per pixel (or bytes per block if compressed) */
- GLuint num_samples;
bool compressed;
- /**
- * Level zero image dimensions. These dimensions correspond to the
- * logical width, height, and depth of the texture as seen by client code.
- * Accordingly, they do not account for the extra width, height, and/or
- * depth that must be allocated in order to accommodate multisample
- * formats, nor do they account for the extra factor of 6 in depth that
- * must be allocated in order to accommodate cubemap textures.
- */
- uint32_t logical_width0, logical_height0, logical_depth0;
-
- /**
- * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
- * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
- */
- enum miptree_array_layout array_layout;
+ /* Includes image offset tables: */
+ struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
/**
- * The distance in between array slices.
+ * Offset into bo where the surface starts.
*
- * The value is the one that is sent in the surface state. The actual
- * meaning depends on certain criteria. Usually it is simply the number of
- * uncompressed rows between each slice. However on Gen9+ for compressed
- * surfaces it is the number of blocks. For 1D array surfaces that have the
- * mipmap tree stored horizontally it is the number of pixels between each
- * slice.
- */
- uint32_t qpitch;
-
- /**
- * MSAA layout used by this buffer.
- */
- enum intel_msaa_layout msaa_layout;
-
- /* Derived from the above:
- */
- GLuint total_width;
- GLuint total_height;
-
- /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
- * this depth mipmap tree, if any.
- */
- uint32_t depth_clear_value;
-
- /* Includes image offset tables:
- */
- struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
-
- /* Offset into bo where miptree starts:
+ * @see intel_mipmap_tree::bo
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
*/
uint32_t offset;
/**
* \brief HiZ aux buffer
*
- * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
- * buffer, use intel_miptree_alloc_hiz().
+ * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
*
* To determine if hiz is enabled, do not check this pointer. Instead, use
- * intel_miptree_slice_has_hiz().
+ * intel_miptree_level_has_hiz().
*/
struct intel_miptree_aux_buffer *hiz_buf;
/**
- * \brief Map of miptree slices to needed resolves.
+ * \brief The type of auxiliary compression used by this miptree.
*
- * This is used only when the miptree has a child HiZ miptree.
+ * This describes the type of auxiliary compression that is intended to be
+ * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that
+ * auxiliary compression is permanently disabled. An aux usage other than
+ * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
+ * been allocated nor does it imply that auxiliary compression will always
+ * be enabled for this surface. For instance, with CCS_D, we may allocate
+ * the CCS on-the-fly and it may not be used for texturing if the miptree
+ * is fully resolved.
+ */
+ enum isl_aux_usage aux_usage;
+
+ /**
+ * \brief Whether or not this miptree supports fast clears.
+ */
+ bool supports_fast_clear;
+
+ /**
+ * \brief Maps miptree slices to their current aux state
*
- * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
- * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
- * mt->hiz_mt->hiz_map, is unused.
+ * This two-dimensional array is indexed as [level][layer] and stores an
+ * aux state for each slice.
*/
- struct exec_list hiz_map; /* List of intel_resolve_map. */
+ enum isl_aux_state **aux_state;
/**
* \brief Stencil miptree for depthstencil textures.
* require separate stencil. It always has the true copy of the stencil
* bits, regardless of mt->format.
*
+ * \see 3DSTATE_STENCIL_BUFFER
* \see intel_miptree_map_depthstencil()
* \see intel_miptree_unmap_depthstencil()
*/
struct intel_mipmap_tree *stencil_mt;
/**
- * \brief MCS miptree.
+ * \brief Stencil texturing miptree for sampling from a stencil texture
*
- * This miptree contains the "multisample control surface", which stores
- * the necessary information to implement compressed MSAA
- * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
+ * Some hardware doesn't support sampling from the stencil texture as
+ * required by the GL_ARB_stencil_texturing extenion. To workaround this we
+ * blit the texture into a new texture that can be sampled.
*
- * NULL if no MCS miptree is in use for this surface.
+ * \see intel_update_r8stencil()
*/
- struct intel_mipmap_tree *mcs_mt;
+ struct intel_mipmap_tree *r8stencil_mt;
+ bool r8stencil_needs_update;
/**
- * Fast clear state for this buffer.
+ * \brief MCS auxiliary buffer.
+ *
+ * This buffer contains the "multisample control surface", which stores
+ * the necessary information to implement compressed MSAA
+ * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
+ *
+ * NULL if no MCS buffer is in use for this surface.
*/
- enum intel_fast_clear_state fast_clear_state;
+ struct intel_miptree_aux_buffer *mcs_buf;
/**
- * The SURFACE_STATE bits associated with the last fast color clear to this
- * color mipmap tree, if any.
- *
- * This value will only ever contain ones in bits 28-31, so it is safe to
- * OR into dword 7 of SURFACE_STATE.
+ * Planes 1 and 2 in case this is a planar surface.
*/
- uint32_t fast_clear_color_value;
+ struct intel_mipmap_tree *plane[2];
/**
- * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
- * buffer. This is useful for sharing the miptree bo with an external client
- * that doesn't understand auxiliary buffers.
+ * Fast clear color for this surface. For depth surfaces, the clear value
+ * is stored as a float32 in the red component.
*/
- bool disable_aux_buffers;
+ union isl_color_value fast_clear_color;
/* These are also refcounted:
*/
GLuint refcount;
};
-void
-intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
- unsigned *width_px, unsigned *height);
bool
-intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling);
-bool
-intel_miptree_is_fast_clear_capable(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-bool
-intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
+intel_miptree_alloc_ccs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
- MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1,
+ MIPTREE_LAYOUT_GEN6_HIZ_STENCIL = 1 << 1,
MIPTREE_LAYOUT_FOR_BO = 1 << 2,
MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y |
MIPTREE_LAYOUT_TILING_NONE,
+
+ MIPTREE_LAYOUT_FOR_SCANOUT = 1 << 7,
};
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
- drm_intel_bo *bo,
+ struct brw_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
int pitch,
uint32_t layout_flags);
-void
+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+ __DRIimage *image,
+ GLenum target,
+ enum isl_colorspace colorspace,
+ bool is_winsys_image);
+
+bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- drm_intel_bo *bo,
+ struct intel_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch);
intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
/** \brief Assert that the level and layer are valid for the miptree. */
-static inline void
-intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
+void
+intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
uint32_t level,
- uint32_t layer)
-{
- (void) mt;
- (void) level;
- (void) layer;
-
- assert(level >= mt->first_level);
- assert(level <= mt->last_level);
- assert(layer < mt->level[level].depth);
-}
+ uint32_t layer);
void intel_miptree_reference(struct intel_mipmap_tree **dst,
struct intel_mipmap_tree *src);
GLuint level, GLuint slice,
GLuint *x, GLuint *y);
+enum isl_surf_dim
+get_isl_surf_dim(GLenum target);
+
+enum isl_dim_layout
+get_isl_dim_layout(const struct gen_device_info *devinfo,
+ enum isl_tiling tiling, GLenum target);
+
+enum isl_aux_usage
+intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt);
+
void
intel_get_image_dims(struct gl_texture_image *image,
int *width, int *height, int *depth);
void
-intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
- bool map_stencil_as_y_tiled,
+intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
uint32_t *mask_x, uint32_t *mask_y);
void
-intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
uint32_t *tile_w, uint32_t *tile_h);
uint32_t
uint32_t *tile_y);
uint32_t
intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
- uint32_t x, uint32_t y,
- bool map_stencil_as_y_tiled);
+ uint32_t x, uint32_t y);
-void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
- GLuint level,
- GLuint x, GLuint y, GLuint d);
-
-void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
- GLuint level,
- GLuint img, GLuint x, GLuint y);
+void
+intel_miptree_copy_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned src_layer,
+ struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned dst_layer);
void
intel_miptree_copy_teximage(struct brw_context *brw,
* functions on a miptree without HiZ. In that case, each function is a no-op.
*/
-bool
-intel_miptree_wants_hiz_buffer(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
struct intel_mipmap_tree *mt);
bool
-intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
+intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
-void
-intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
- uint32_t level,
- uint32_t depth);
-void
-intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
- uint32_t level,
- uint32_t depth);
-
-void
-intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
- uint32_t level);
+/**\}*/
-/**
- * \return false if no resolve was needed
- */
bool
-intel_miptree_slice_resolve_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int depth);
+intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
+ unsigned start_level, unsigned num_levels,
+ unsigned start_layer, unsigned num_layers);
-/**
- * \return false if no resolve was needed
- */
-bool
-intel_miptree_slice_resolve_depth(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int depth);
-/**
- * \return false if no resolve was needed
- */
-bool
-intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
+#define INTEL_REMAINING_LAYERS UINT32_MAX
+#define INTEL_REMAINING_LEVELS UINT32_MAX
-/**
- * \return false if no resolve was needed
+/** Prepare a miptree for access
+ *
+ * This function should be called prior to any access to miptree in order to
+ * perform any needed resolves.
+ *
+ * \param[in] start_level The first mip level to be accessed
+ *
+ * \param[in] num_levels The number of miplevels to be accessed or
+ * INTEL_REMAINING_LEVELS to indicate every level
+ * above start_level will be accessed
+ *
+ * \param[in] start_layer The first array slice or 3D layer to be accessed
+ *
+ * \param[in] num_layers The number of array slices or 3D layers be
+ * accessed or INTEL_REMAINING_LAYERS to indicate
+ * every layer above start_layer will be accessed
+ *
+ * \param[in] aux_supported Whether or not the access will support the
+ * miptree's auxiliary compression format; this
+ * must be false for uncompressed miptrees
+ *
+ * \param[in] fast_clear_supported Whether or not the access will support
+ * fast clears in the miptree's auxiliary
+ * compression format
*/
-bool
-intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
+void
+intel_miptree_prepare_access(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t start_level, uint32_t num_levels,
+ uint32_t start_layer, uint32_t num_layers,
+ enum isl_aux_usage aux_usage,
+ bool fast_clear_supported);
+
+/** Complete a write operation
+ *
+ * This function should be called after any operation writes to a miptree.
+ * This will update the miptree's compression state so that future resolves
+ * happen correctly. Technically, this function can be called before the
+ * write occurs but the caller must ensure that they don't interlace
+ * intel_miptree_prepare_access and intel_miptree_finish_write calls to
+ * overlapping layer/level ranges.
+ *
+ * \param[in] level The mip level that was written
+ *
+ * \param[in] start_layer The first array slice or 3D layer written
+ *
+ * \param[in] num_layers The number of array slices or 3D layers
+ * written or INTEL_REMAINING_LAYERS to indicate
+ * every layer above start_layer was written
+ *
+ * \param[in] written_with_aux Whether or not the write was done with
+ * auxiliary compression enabled
+ */
+void
+intel_miptree_finish_write(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t num_layers,
+ enum isl_aux_usage aux_usage);
-/**\}*/
+/** Get the auxiliary compression state of a miptree slice */
+enum isl_aux_state
+intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
+ uint32_t level, uint32_t layer);
+
+/** Set the auxiliary compression state of a miptree slice range
+ *
+ * This function directly sets the auxiliary compression state of a slice
+ * range of a miptree. It only modifies data structures and does not do any
+ * resolves. This should only be called by code which directly performs
+ * compression operations such as fast clears and resolves. Most code should
+ * use intel_miptree_prepare_access or intel_miptree_finish_write.
+ */
+void
+intel_miptree_set_aux_state(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t num_layers,
+ enum isl_aux_state aux_state);
/**
- * Update the fast clear state for a miptree to indicate that it has been used
- * for rendering.
+ * Prepare a miptree for raw access
+ *
+ * This helper prepares the miptree for access that knows nothing about any
+ * sort of compression whatsoever. This is useful when mapping the surface or
+ * using it with the blitter.
*/
static inline void
-intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
+intel_miptree_access_raw(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t level, uint32_t layer,
+ bool write)
{
- /* If the buffer was previously in fast clear state, change it to
- * unresolved state, since it won't be guaranteed to be clear after
- * rendering occurs.
- */
- if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
- mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
+ intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
+ if (write)
+ intel_miptree_finish_write(brw, mt, level, layer, 1, false);
}
+enum isl_aux_usage
+intel_miptree_texture_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ enum isl_format view_format);
+void
+intel_miptree_prepare_texture(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ enum isl_format view_format,
+ bool *aux_supported_out);
void
-intel_miptree_resolve_color(struct brw_context *brw,
+intel_miptree_prepare_image(struct brw_context *brw,
struct intel_mipmap_tree *mt);
+void
+intel_miptree_prepare_fb_fetch(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t num_layers);
+enum isl_aux_usage
+intel_miptree_render_aux_usage(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ bool srgb_enabled, bool blend_enabled);
+void
+intel_miptree_prepare_render(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t layer_count,
+ bool srgb_enabled, bool blend_enabled);
+void
+intel_miptree_finish_render(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t layer_count,
+ bool srgb_enabled, bool blend_enabled);
+void
+intel_miptree_prepare_depth(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t layer_count);
+void
+intel_miptree_finish_depth(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t layer_count,
+ bool depth_written);
void
intel_miptree_make_shareable(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
-/**
- * Horizontal distance from one slice to the next in the two-dimensional
- * miptree layout.
- */
-unsigned
-brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned level);
-
-/**
- * Vertical distance from one slice to the next in the two-dimensional miptree
- * layout.
- */
-unsigned
-brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned level);
-
void
+intel_update_r8stencil(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+
+bool
brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags);
unsigned int level,
unsigned int slice);
-void
-intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op op);
+bool
+intel_miptree_sample_with_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
#ifdef __cplusplus
}
projects / mesa.git / blobdiff