#include <assert.h>
-#include "intel_regions.h"
+#include "main/mtypes.h"
+#include "intel_bufmgr.h"
#include "intel_resolve_map.h"
#include <GL/internal/dri_interface.h>
extern "C" {
#endif
+struct brw_context;
struct intel_renderbuffer;
struct intel_resolve_map;
*/
GLuint depth;
+ /**
+ * \brief Is HiZ enabled for this level?
+ *
+ * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
+ * allocated and (2) the HiZ memory for the slices in this level reside at
+ * \c mt->hiz_mt->level[l].
+ */
+ bool has_hiz;
+
/**
* \brief List of 2D images in this mipmap level.
*
* intel_miptree_map/unmap on this slice.
*/
struct intel_miptree_map *map;
-
- /**
- * \brief Is HiZ enabled for this slice?
- *
- * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
- * has been allocated and (2) the HiZ memory corresponding to this slice
- * resides at \c mt->hiz_mt->level[l].slice[s].
- */
- bool has_hiz;
} *slice;
};
INTEL_FAST_CLEAR_STATE_CLEAR,
};
+enum miptree_array_layout {
+ /* Each array slice contains all miplevels packed together.
+ *
+ * Gen hardware usually wants multilevel miptrees configured this way.
+ *
+ * A 2D Array texture with 2 slices and multiple LODs using
+ * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
+ *
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * +---+ +-+
+ * | | +-+
+ * +---+ *
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * +---+ +-+
+ * | | +-+
+ * +---+ *
+ */
+ ALL_LOD_IN_EACH_SLICE,
+
+ /* Each LOD contains all slices of that LOD packed together.
+ *
+ * In some situations, Gen7+ hardware can use the array_spacing_lod0
+ * feature to save space when the surface only contains LOD 0.
+ *
+ * Gen6 uses this for separate stencil and hiz since gen6 does not support
+ * multiple LODs for separate stencil and hiz.
+ *
+ * A 2D Array texture with 2 slices and multiple LODs using
+ * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
+ *
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * +---+ +-+
+ * | | +-+
+ * +---+ +-+
+ * | | :
+ * +---+
+ */
+ ALL_SLICES_AT_EACH_LOD,
+};
+
+/**
+ * Miptree aux buffer. These buffers are associated with a miptree, but the
+ * format is managed by the hardware.
+ *
+ * For Gen7+, we always give the hardware the start of the buffer, and let it
+ * handle all accesses to the buffer. Therefore we don't need the full miptree
+ * layout structure for this buffer.
+ *
+ * For Gen6, we need a hiz miptree structure for this buffer so we can program
+ * offsets to slices & miplevels.
+ */
+struct intel_miptree_aux_buffer
+{
+ /** Buffer object containing the pixel data. */
+ drm_intel_bo *bo;
+
+ uint32_t pitch; /**< pitch in bytes. */
+
+ uint32_t qpitch; /**< The distance in rows between array slices. */
+
+ struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
+};
+
struct intel_mipmap_tree
{
/** Buffer object containing the pixel data. */
* MESA_FORMAT_Z24_UNORM_X8_UINT.
*
* For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
- * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
+ * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
*/
mesa_format format;
uint32_t logical_width0, logical_height0, logical_depth0;
/**
- * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
- * if the surface only contains LOD 0, and hence no space is for LOD's
- * other than 0 in between array slices.
- *
- * Corresponds to the surface_array_spacing bit in gen7_surface_state.
+ * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
+ * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
*/
- bool array_spacing_lod0;
+ enum miptree_array_layout array_layout;
/**
* The distance in rows between array slices in an uncompressed surface.
uint32_t offset;
/**
- * \brief HiZ miptree
+ * \brief HiZ aux buffer
*
* The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
- * miptree, use intel_miptree_alloc_hiz().
+ * buffer, use intel_miptree_alloc_hiz().
*
* To determine if hiz is enabled, do not check this pointer. Instead, use
* intel_miptree_slice_has_hiz().
*/
- struct intel_mipmap_tree *hiz_mt;
+ struct intel_miptree_aux_buffer *hiz_buf;
/**
* \brief Map of miptree slices to needed resolves.
* \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
* mt->hiz_mt->hiz_map, is unused.
*/
- struct intel_resolve_map hiz_map;
+ struct exec_list hiz_map; /* List of intel_resolve_map. */
/**
* \brief Stencil miptree for depthstencil textures.
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode);
+ enum intel_miptree_tiling_mode,
+ bool force_all_slices_at_each_lod);
struct intel_mipmap_tree *
intel_miptree_create_layout(struct brw_context *brw,
GLuint height0,
GLuint depth0,
bool for_bo,
- GLuint num_samples);
+ GLuint num_samples,
+ bool force_all_slices_at_each_lod);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t offset,
uint32_t width,
uint32_t height,
+ uint32_t depth,
int pitch);
void
struct intel_mipmap_tree *mt);
bool
-intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
- uint32_t level,
- uint32_t layer);
+intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
void
intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
unsigned int h,
GLbitfield mode,
void **out_ptr,
- int *out_stride);
+ ptrdiff_t *out_stride);
void
intel_miptree_unmap(struct brw_context *brw,